A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology

Advanced memory concepts for DRAM and nonvolatile memories

“…As scaling advances, the area available for capacitor decreases. Therefore, capacitance enhancement technologies such as hemispherical silicon grains and Al 2 O 3 ALD high k dielectric are promising candidate [7]. DRAM scaling will continue to integrate many advanced technologies in view of the huge size of the DRAM market.…”

New Materials in Memory Development Sub 50 nm: Trends in Flash and DRAM

“…Here, capacitance enhancement was reached by surface area enhancement due to improved aspect ratio etches (up to 70:1), introduction of hemispherical grains and bottle-shaped trenches. [21] The required EOT of a stacked capacitor is shown in Figure 11. Based on improvements in high-k materials, the EOT of stacked capacitor dielectric was shrunk from EOT ¼ 1.5 nm at 80 nm groundrule to EOT ¼ 1.0 nm at 55 nm ground rule; the trend will continue towards EOT ¼ 0.5 nm at 40 nm groundrule (base for this estimate: storage node height 1.4 mm).…”

Oxide-Nitride Storage Dielectric Formation in a Single-Furnace Process for Trench DRAM

“…To address the latter problem, the introduction of the high-k dielectric materials such as the Al 2 O 3 [1], HfSiO [2], HfAlO x [3], and HfO 2 /Ta 2 O 5 stack [4], along with the hemispherical-silicongrain (HSG) structure is an ineluctable trend. Nevertheless, the aforementioned avenues offer opportunities to boost the cell capacitance for the upcoming generations; unfortunately, it is not true for the 8-in fab since most of the DRAM chipmakers concentrate the advanced-equipment investment on the 12-in fab.…”