New Materials in Memory Development Sub 50 nm: Trends in Flash and DRAM

Abstract

New materials are of key importance for scaling memories in the sub 50 nm generations. Currently high‐k materials and metal gates are investigated for usage in Flash and DRAM memory. However, the requirements in the applications are different, leading to different material combinations. This paper gives an overview on new materials with focus on memory applications.

Structure and morphology of Ru films grown by atomic layer deposition from 1-ethyl-1’-methyl-ruthenocene

“…Moreover, studies on atomic layer deposition of Ru from advanced precursors such as (methylcyclopentadienyl)(pyrrolyl)ruthenium on SrTiO 3 [15] have revealed that the growth of Ru on such materials is poorly controlled unless plasma-assisted cleaning of underlying oxide film is applied despite the possible structural damage of the oxide surface. Nevertheless, noble metal electrodes (Ru, RuO 2 ) are of significant importance [16,17] despite the related increase in processing costs. Notable amount of studies on Ru so far have been devoted to the issues related to the nucleation of ruthenium thin films as well as to the parametrization of growth processdependence of the growth rate and roughness on growth temperature, pressure and time [2,[18][19][20][21].…”

Novel materials by atomic layer deposition and molecular layer deposition

“…Currently, the capacitance equivalent thickness (CET) requirement in DRAMs for the oxide fi lm is below 1 nm and will decrease to 0.5 nm in the near future, while keeping the leakage current density below 10 -7 A/cm 2 at 1 V. 4 At the moment, the most widely used dielectric material in DRAMs is an ALD-formed ZrO 2 -Al 2 O 3 -ZrO 2 nanolaminate. 5 The transition of ALD high-κ oxides to the product level required extensive research and development, including the analysis of a wide range of precursor materials and processes. Most of the attention has been devoted to hafnium and zirconium oxides, but rare-earth metal oxides and other doping systems have also been studied.…”

Atomic Layer Deposition of High‐k Oxides of the Group 4 Metals for Memory Applications

“…[11] However, in a few years with a design rule of <40 nm, the CET must be lowered to <0.5 nm while keeping the leakage current density below 10 À7 A cm À2 at 1 V in the metal-insulator-metal (MIM) structures. [4] The selection of high-k materials for these requirements is challenging.…”

“…More detailed discussion on current trends in new materials for memory development, including flash technology and logic devices in DRAM technology, is given in another article in this special issue. [11] 4. ALD of Binary and Ternary High-k Dielectrics Oxides of Group 4 metals…”

“…This result is very promising, although lower CET with low leakage is needed for realizing clear improvement over, for example, ZAZ-based MIM structures. [11] Further studies from the same group showed impressive results: CET as low as 0.48 nm with 10 À7 A cm À2 leakage at 0.8 V was achieved simply by incorporating small amounts of Al 2 O 3 into the TiO 2 film. [28] Doping with 8% of Al 3þ cations enabled five orders of magnitude lower leakage than obtained by the corresponding undoped TiO 2 films (Figure 3).…”