Proceedings of IEEE International Electron Devices Meeting
DOI: 10.1109/iedm.1993.347399
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A highly manufacturable trench isolation process for deep submicron DRAMs

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Cited by 16 publications
(5 citation statements)
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“…If high fields must be tolerated, it may be necessary to (1) develop field insulators that are not significantly affected by high-field irradiation, or (2) reduce the effect of charge buildup in the field oxide by increasing the threshold voltage of the parasitic field oxide transistors. The field threshold voltage can be increased by pulling back the source and drain regions (n+ implants) from the trench edges andor increasing the sidewall doping (p+ implant) [10,12,13]. (This is similar to the approach of forming guardbands that was used in early radiation hardened CMOS technologies.)…”
Section: Id Resultsmentioning
confidence: 99%
“…If high fields must be tolerated, it may be necessary to (1) develop field insulators that are not significantly affected by high-field irradiation, or (2) reduce the effect of charge buildup in the field oxide by increasing the threshold voltage of the parasitic field oxide transistors. The field threshold voltage can be increased by pulling back the source and drain regions (n+ implants) from the trench edges andor increasing the sidewall doping (p+ implant) [10,12,13]. (This is similar to the approach of forming guardbands that was used in early radiation hardened CMOS technologies.)…”
Section: Id Resultsmentioning
confidence: 99%
“…On the one hand, oxidation makes LOCOS easy to manufacture because isolation areas are created with a single oxidation step. There are also additional limitations of using LOCOS, including doping encroachment, susceptibility to latch-up, and oxidation-induced stress in the substrate [8][9][10]. First of all, 56 % of the oxide is situated above the silicon surface where it does not serve as isolation, but still creates additional topography of several hundred nanometers on the wafer surface.…”
Section: Locos To Stimentioning
confidence: 99%
“…Although initially there were doubts about the scalability of the technology beyond 1 mm, ingenious approaches such as polybuffered LOCOS [11] and polybuffered recessed LOCOS [12] extended it even to 0.25 mm [10]. Such a technology is shallow trench isolation, which relies on reactive ion etching (RIE) and chemical vapor deposition (CVD) oxide filled trenches as isolation rather than areas formed by oxidation.…”
Section: Locos To Stimentioning
confidence: 99%
“…In the ULSI era the isolation technology is transforming from LOCOS to shallow trench in order to satisfy increasing requirements as abrupt transition of active/field region, good planar surface, and reduced junction capacitance (see, for example, [1][2][3]). Unfortunately, large mechanical stress and damage in STI, eventually enhanced by subsequent processing, generate dislocations.…”
Section: Introductionmentioning
confidence: 99%