A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Chen, Chih‐Ping; Lue, Hang-Ting; Chang, Kai‐Chun; Hsiao, Yi‐Hsuan; Hsieh, Chih-Chang; Chen, Shih-Hung; Shih, Yung‐Feng; Hsieh, Kuang-Yeu; Yang, Tahone; Chen, Kuang-Chao; Lu, Chih‐Yuan

doi:10.1109/vlsit.2012.6242476

Cited by 21 publications

(19 citation statements)

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“…The 3D Vertical Gate (3D VG-type) NAND architecture (Horizontal Channel structure) has been investigated and extensively studied, being the following references only a small example of related publications [8,10,[18][19][20][21][22][23][24][25]. The scalability of the architecture has been studied down to the 2× nm node.…”

Section: Vg-type 3d Nand Architecturementioning

confidence: 99%

3D VG-Type NAND Flash Memories

Silvagni

2016

3D Flash Memories

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Solid State Disk applications have been the main drivers for the cost reduction of NAND Flash memory. Technology scaling limits have been almost reached and new directions were investigated for a decade. 3D NAND appeared as the most promising and short term viable solution to the scaling problem. 3D NAND offers the possibility to keep scaling memory density beyond 2D NAND 1z nm technology and opens new landscapes if the technology hurdles can be definitely overcome. Additionally Multi bit per cell technology is applicable to 3D NAND as well; therefore, the storage capacity growth trend is not going to meet the inflection point soon. Big Data storage demand remains certainly the driver for the rapidity of 3D NAND to become industry mainstream.With respect to the flat 2D NAND Flash, three-dimensional architectures demand a more challenging approach to deal with process, design architectures, parasitic effects, testing. At the time of writing this chapter, 3D technology is moving into production inside solid state storage solutions; however, those NAND chips aren't commercially available as raw components. 3D NAND chips are used by vertically integrated manufacturers and few partners to build the storage systems under a strict control on the usage. Technology solutions are still diversified among the few players in the 3D arena and no unique mainstream solution is emerged yet.In this chapter the principal architectural pieces of 3D NAND will be reviewed putting the focus on one of them: VG-Type, Vertical Gate 3D NAND.

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Section: Vg-type 3d Nand Architecturementioning

confidence: 99%

3D VG-Type NAND Flash Memories

Silvagni

2016

3D Flash Memories

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“…Figure 8 shows the recent published 37.5nm half pitch 3D VG NAND [8]. Further pitch scalability seems feasible in this architecture.…”

Section: Processing Feasibilitymentioning

confidence: 99%

“…3D NAND Flash [1][2][3][4][5][6][7][8][9] has attracted much attention in recent years. In principle, 3D NAND Flash allows bigger cell size to relax the device scaling limitation of FG NAND.…”

Section: Introductionmentioning

confidence: 99%

“…The most popular structures are based on nano-wire vertical channel (VC) device [1][2][3][4], where channel current flows vertically but gate is horizontally shared. An alternative is the vertical gate (VG) [5][6][7][8][9], where channel current flows horizontally but gate is vertically shared. Charge-trapping SONOS (and MANOS) devices are the most preferred because of easier process integration and smaller cell size.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, VG NAND has better pitch scalability than VC NAND. A 37.5nm half pitch device has been demonstrated [8,9]. If VG NAND can further scale the half pitch to 25nm, a 32-layer memory with MLC (2bit/cell) already offers a 1Tb memory and this is very promising.…”

Section: Introductionmentioning

confidence: 99%

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Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

Lue

Chen

Shih

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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This paper provides an overview of 3D NAND Flash memory architecture and a comprehensive study on various array decoding methods of vertical gate (VG) NAND Flash. A certain memory density may be achieved by any array architecture but with different numbers of stacking layers. A smaller pitch allows the achieving of high density at reasonable number of stacked memory layers ( ≤ 32) and thus potentially offers lower cost. VG NAND has good pitch scalability thus is very attractive. On the other hand, it is more difficult to decode the bit line in a VG architecture, thus decoding innovations are required for a compact array architecture design. This paper provides a systematic comparison of four different decoding methods of VG NAND. Performance of the TFT BE-SONOS device used in 3D VG NAND is also addressed.

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Vertical NAND Flash

2014

Vertical 3D Memory Technologies

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A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Cited by 21 publications

References 0 publications

3D VG-Type NAND Flash Memories

3D VG-Type NAND Flash Memories

Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

Vertical NAND Flash

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