A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm&lt;sup&gt;2&lt;/sup&gt; per MB

Kuo, Ming-Zhang; Takahashi, Osamu; Yang, Ping-Lin; Lin, Cheng-Chung; Wang, Min-Jer; Wang, Ping-Wei; Dhong, S.H.

doi:10.1109/cicc.2013.6658452

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference 2013

DOI: 10.1109/cicc.2013.6658452

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A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm<sup>2</sup> per MB

Ming-Zhang Kuo

Osamu Takahashi

Ping-Lin Yang

et al.

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A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm<sup>2</sup> per MB

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