A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes

Nibhanupudi, S. S. Teja; Prasad, Divya; Das, Shidhartha; Zografos, Odysseas; Robinson, Alex; Gupta, Anshul; Spessot, A.; Debacker, Peter; Verkest, D.; Ryckaert, Julien; Hellings, Geert; Myers, James R.; Cline, Brian; Kulkarni, Jaydeep P.

doi:10.1109/ted.2022.3186657

Cited by 14 publications

(2 citation statements)

References 14 publications

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“…3 Scaled cell heights stalemated the frontside power and ground (PG) rails at the standard cell boundaries, where the PG rails were deeply scaled, since highly resistive (e.g. 900 Ω/µm) 4 but still relatively wider than their routing track counterparts. Overall, the less number of routing resources and highly resistive PG rails were significantly derating the design Quality of Results metrics, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…the routing congestion rate and the IR drop level. 4 Under the aforementioned circumstances, the BSPDN concept has been proposed 5,6 to further boost the logic scaling by relieving the available routing track resources, as well as to leverage the usage of wider pitched, hence lower resistance backside metal rails. Since its proposal, the BSPDN concept has gained attention.…”

Section: Introductionmentioning

confidence: 99%

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High-density standard cell libraries with backside power options in A14 nanosheet node

Kukner,

Mirabelli,

Yang

et al. 2024

DTCO and Computational Patterning III

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Beyond FinFET device nodes, nanosheet is the next transistor architecture in CMOS scaling roadmaps. On top of the newer device architectures and materials, several other CMOS scaling boosters are being considered, and can help in further to improve the power, performance and area scaling.Backside power delivery network (BSPDN) is one of the promising scaling boosters, e.g. it disengages metal routing resources from the frontside, resulting in a lower routing congestion. Hence, the BSPDN booster paves the way for higher frequency and lower area footprint. However, ad-hoc standard cell design and optimization is required to connect the BSPDN network to the logic devices located in the front-end-of-line (FEOL).In this study, the implementation of different connection options to the BSPDN are studied in imec's A14 nanosheet node: i.e. Through Silicon Via in the Middle of Line (TSVM), buried power rail (BPR) and direct backside contact (BSC). The different implications on standard cell design, as cell track height, routing and main process challenges are then compared to the classic frontside power delivery option.Finally, high-density (HD) standard cell libraries are implemented and characterized. Normalized area and delay comparisons at the library-level are presented. Area gains can rise up to 25% in case of BSC BSPDN option. Furthermore, maximum delay gains can vary up to 20% depending on standard cell type.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-density standard cell libraries with backside power options in A14 nanosheet node

Kukner,

Mirabelli,

Yang

et al. 2024

DTCO and Computational Patterning III

View full text Add to dashboard Cite

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Digital Etching of Molybdenum Interconnects Using Plasma Oxidation

Erofeev,

Hartanto,

Khan

et al. 2024

Adv Materials Inter

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Molybdenum (Mo) has a high potential of becoming the material of choice for sub‐10 nm scale metal structures in future integrated circuits (ICs). Manufacturing at this scale requires exceptional precision and consistency, so many metal processing techniques must be reconsidered. In particular, present direct wet chemical etching methods produce anisotropic etching profiles with significant surface roughness, which can be detrimental to device performance. Here, it is shown that polycrystalline Mo nanowires can be etched uniformly using a cyclic two‐step “digital” method: the metal surface is first oxidized with isotropic oxygen plasma to form a layer of MoO3, which is then selectively removed using either wet chemical or dry isotropic plasma etching. These two steps are repeated in cycles until the intended metal recess is achieved. High uniformity of plasma oxidation defines the etching uniformity, and small metal recess per cycle (typically 1–2 nm) provides precise control over the etching depth. This method can replace wet etching where high etching precision is needed, enabling the reliable manufacturing of nanoscale metal interconnects.

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Solving the Annealing of Mo Interconnects for Next‐Gen Integrated Circuits

Erofeev,

Hartanto,

Saidov

et al. 2024

Adv Elect Materials

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Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated circuits. Metal interconnects in their current form struggle to follow the size downscaling due to materials limitations at the nanoscale, causing severe performance losses. Next‐generation interconnects need new materials, and molybdenum (Mo) is considered the best choice, offering low resistivity, good scalability, and barrierless integration at a low cost. However, it requires annealing at temperatures far exceeding the currently accepted limit. In this work, the challenges of high‐temperature annealing of patterned Mo nanowires are looked into, and a new approach is presented to overcome them. It is demonstrated that while a conventional annealing process improves the average grain size, it can also reduce the cross‐section area, thus increasing the resistivity. Using high‐resolution transmission electron microscopy (TEM) with in situ heating, the evolution of structural features in real time is directly observed. Using insights from these experiments, a cyclic pulsed annealing method is developed, and it is shown that the desired grain structure is achieved in only a few seconds, without forming the surface grooves. These findings can radically facilitate Mo integration, boosting the efficiency of future integrated circuits.

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A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes

Cited by 14 publications

References 14 publications

High-density standard cell libraries with backside power options in A14 nanosheet node

High-density standard cell libraries with backside power options in A14 nanosheet node

Digital Etching of Molybdenum Interconnects Using Plasma Oxidation

Solving the Annealing of Mo Interconnects for Next‐Gen Integrated Circuits

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