A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing

Wu, Youfeng; Hu, Shiliang; Borin, Edson; Wang, Cheng

doi:10.1109/cgo.2011.5764691

Cited by 10 publications

(8 citation statements)

References 22 publications

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“…We distinguish our work from single-ISA, heterogeneous implementation efforts [27], [30], [42], [38], as 10x10 pursues a more radically heterogeneous agenda with finer-grained, rigorous separation. [14] show that as much as 100-fold improvements may be possible if breaking down traditional "general register" architectures with orthogonal operations and single memories are contemplated.…”

Section: Discussion and Related Workmentioning

confidence: 99%

Systematic evaluation of workload clustering for extremely energy-efficient architectures

Guha

Zhang

Rasool

et al. 2013

SIGARCH Comput. Archit. News

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Chip power consumption has reached its limits, leading to the flattening of single-core performance. We propose the 10x10 processor, a federated heterogeneous multi-core architecture, where each core is an ensemble of u-engines (micro-engines, similar to accelerators) specialized for different workload groups to achieve dramatically higher energy efficiency. The u-engines collectively target the entire general-purpose workload space.The problem we study in this article is selecting the set of workloads that each u-engine should be customized for. For this problem we study the computation structure of a wide variety of workloads and cluster together workloads with similar computation structures, the idea being that each u-engine will be customized for the compute structures exhibited by a particular cluster. The constraint on this problem is the silicon budget of a processor. Lower silicon budgets accommodate fewer uengines and require individual u-engines to target larger segments of the workload space which leads to lower energy efficiency benefits from customization, because there is more variation among the compute structures making up each cluster. Therefore, we also study how workload coverage and benefit can be maximized for a given silicon budget.We study a broad general-purpose workload that includes 34 codes from 6 benchmark suites, identifying the most frequent functions, and clustering them based on two sets of instruction usage features (high-resolution and low-resolution) into 8, 16, 32, 64, 128 clusters respectively. We develop abstract metrics (coverage and weighted customization benefit) to evaluate the clusters. We show significant potential payoffs with four benefit models: 2-3x (square root model), 4-10x (linear model), 12-24x (quadratic model), and 22-26x (cubic model).

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Section: Discussion and Related Workmentioning

confidence: 99%

Systematic evaluation of workload clustering for extremely energy-efficient architectures

Guha

Zhang

Rasool

et al. 2013

SIGARCH Comput. Archit. News

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“…Executing code regions of certain characteristics to suitable cores in heterogeneous multicore systems composed of cores with different points of energy/performance sharing the same ISA to save energy has been explored in [23,26,36]. Another approach to energyefficient computing is to exploit the DVFS capability of modern processors [3,35].…”

Section: Related Workmentioning

confidence: 99%

“…To get the energy benefits of matching processing speed to IO rates, two common techniques are: 1) To consolidate tasks by relocating tasks to fewer cores to improve core utilization and enable turning off idle cores [2,31]; 2) To vary processing speed by applying dynamic voltage and frequency scaling(DVFS) [3,9,16,35] or processor composition [8,21] or heterogeneous processors of different speeds [23,26,36]. Figure 2.…”

Section: Energy Optimizationmentioning

confidence: 99%

StreaMorph: A case for synthesizing energy-efficient adaptive programs using high-level abstractions

Bui

Lee

2013

2013 Proceedings of the International Conference on Embedded Software (EMSOFT)

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This paper presents the concept of adaptive programs, whose computation and communication structures can morph to adapt to environmental and demand changes to save energy and computing resources. In this approach, programmers write one single program using a language at a higher level of abstraction. The compiler will exploit the properties of the abstractions to generate an adaptive program that is able to adjust computation and communication structures to environmental and demand changes.We develop a technique, called StreaMorph, that exploits the properties of stream programs' Synchronous Dataflow (SDF) programming model to enable runtime stream graph transformation. The StreaMorph technique can be used to optimize memory usage and to adjust core utilization leading to energy reduction by turning off idle cores or reducing operating frequencies. The main challenge for such a runtime transformation is to maintain consistent program states by copying states between different stream graph structures, because a stream program optimized for different numbers of cores often has different sets of filters and inter-filter channels. We propose an analysis that helps simplify program state copying processes by minimizing copying of states based on the properties of the SDF model.Finally, we implement the StreaMorph method in the StreamIt compiler. Our experiments on the Intel Xeon E5450 show that using StreaMorph to minimize the number of cores used from eight cores to one core, e.g. when streaming rates become lower, can reduce energy consumption by 76.33% on average. Using StreaMorph to spread workload from four cores to six or seven cores, e.g. when more cores become available, to reduce operating frequencies, can lead to 10% energy reduction. In addition, StreaMorph can lead to a buffer size reduction of 82.58% in comparison with a straightforward inter-core filter migration technique when switching from using eight cores to one core.

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“…• Load balancing in heterogeneous multi-core systems: DBT can be used to translate code from one core to another if cores have di↵erent ISAs [33,55]. If cores share the same ISA, such as in ARM's big.LITTLE [9], hardware extensions remain a feasible approach to virtualization.…”

Section: Comparing Dbt With Hardware Extensionsmentioning

confidence: 99%

Formal virtualization requirements for the ARM architecture

Penneman

Kudinskas

Rawsthorne

et al. 2013

Journal of Systems Architecture

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We present an analysis of the virtualizability of the ARMv7-A architecture carried out in the context of the seminal paper published by Popek and Goldberg 38 years ago. Because their definitions are dated, we first extend their machine model to modern architectures with paged virtual memory, IO and interrupts. We then use our new model to show that ARMv7-A is not classically virtualizable.Insights such as binary translation enable e cient virtualization beyond the original criteria. Companies are also making their architectures virtualizable through extensions. We analyze both approaches for ARM and conclude that both have their use in future systems.

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A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing

Cited by 10 publications

References 22 publications

Systematic evaluation of workload clustering for extremely energy-efficient architectures

Systematic evaluation of workload clustering for extremely energy-efficient architectures

StreaMorph: A case for synthesizing energy-efficient adaptive programs using high-level abstractions

Formal virtualization requirements for the ARM architecture

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