A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

Abstract

A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital-toanalog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm 2 . The ΔΣ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns RMS external clock jitter.

Advanced Class-S transmitter with tri-level delta-sigma modulator

“…The main components of the LPDSM are integrators, latched comparators, DACs, output buffer, a differential clock generator, a bandgap reference, and an on-chip reference. The first and second loop filter is designed using active-RC network for its better linearity than Gm-C filters [8]. The comparator is composed of a preamplifier and a latch.…”

20-MHz bandwidth continuous-time delta-sigma modulator for EPWM transmitter

“…In these applications, the continuous-time DSM (CT-DSM) has received great attention because of the systems require high speed sampling rate with large input bandwidth and inherent anti-alias filtering [11]. However, the experimental results of the CT-DSM usually suffered from the non-ideal effects such as clock jitter sensitivity, DC offset voltage, and processvoltage-temperature variations.…”

Design and measurement of 500-MS/s ΣΔ modulator with half-delayed return-to-zero feedback DAC

“…But, NRZ feedback pulses should be intentionally delayed by a fixed fraction of the sampling period to give the time for the quantizer and DAC [3][4][5]. A certain amount shift of the feedback pulse increases the order of the modulator, thus the loop stability may not be guaranteed under the ELD effect [6]- [7].…”