Design and measurement of 500-MS/s ΣΔ modulator with half-delayed return-to-zero feedback DAC

Abstract

A second-order continuous-time (CT) low-pass ΣΔ modulator using a single feedback digital-to-analog converter (DAC) is presented. To reduce the feedback DACs by one, we introduce half-delayed return-to-zero (HRZ) feedback signaling and feed-forward topology. The HRZ feedback scheme reduces power consumption and die area by removing a summing amplifier and DAC for the excess-loop delay compensation and the feed-forward topology saves additional power and area by replacing the feedback DAC with feed-forward path. The concept is implemented in a 500 MS/s CT ΣΔ modulator for 12-MHz signal bandwidth in a 130 nm CMOS process which occupies 0.19 mm 2 . The Measurements show that the modulator achieves spurious free dynamic range of 61.2 dB, signal-to-noise and distortion ratio of 52.5 dB, and dynamic range of 55 dB. The modulator consumes 9.96 mW at a 1.2 V supply.

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

“…The main difference between the proposed MRZ waveform and the conventional RZ and halfdelayed RZ (HRZ) [15,21,22] waveforms is in the jitter effect of the clock, which is employed to produce these DAC pulses. In the generation of the RZ and HRZ pulses, the two edges of the DAC pulse in a pulse period are affected, independently from each other, by the random fluctuations of the clock edges.…”