A Hybrid Binary-Cascaded Multilevel Inverter With Simple Floating-Capacitor-Voltage Control

Lee, Moonhyun; Yeh, Chih-Shen; Lai, Jih‐Sheng

doi:10.1109/tpel.2020.3007122

Cited by 19 publications

(7 citation statements)

References 17 publications

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“…The optimal methods to generate DC inputs are isolated DC/DC converters and multi tap transformer [19], [28][29][30]. Fig.…”

Section: Viexperimental Resultsmentioning

confidence: 99%

“…where vref is the reference voltage and E1 is the lowest level, and (19) gives the nearest integer. Fig.…”

Section: Iiicontrol Modulation Methodsmentioning

confidence: 99%

“…New structures for multilevel inverters such as hybrid and asymmetrical cascaded multilevel structures have recently appeared to decrease the number of input DC voltage sources [19,20]. However, these structures need specific algorithms to determine the amount of DC voltage sources.…”

Section: Introductionmentioning

confidence: 99%

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A New Asymmetric Cascaded Multilevel Converter Topology With Reduced Voltage Stress and Number of Switches

et al. 2021

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This paper presents a new structure of a multilevel inverter with fewer components, which is suitable for renewable energy sources and industrial loads applications. The structure has three unequal input sources and ten switches that can generate a 15-level output voltage. Furthermore, it can be connected in cascade for increasing, even more, the number of levels and output voltage. The main feature of the proposed inverter is its very low harmonic distortion at the output voltage and current due to the control method, which is based on the nearest level control method for generating a high-quality output voltage. A typical application of this inverter is in solar cells and wind turbines. Both simulations in Matlab/Simulink and experimental results in a scaled-down prototype validate the proposed theoretical analysis.INDEX TERMS Multilevel inverter, cascading converters, low harmonics, losses, distortion.

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“…The optimal methods to generate DC inputs are isolated DC/DC converters and multi tap transformer [19], [28][29][30]. Fig.…”

Section: Viexperimental Resultsmentioning

confidence: 99%

“…where vref is the reference voltage and E1 is the lowest level, and (19) gives the nearest integer. Fig.…”

Section: Iiicontrol Modulation Methodsmentioning

confidence: 99%

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A New Asymmetric Cascaded Multilevel Converter Topology With Reduced Voltage Stress and Number of Switches

et al. 2021

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“…With the same number of cells, a binary-cascaded multilevel inverter (BCMLI) substantially increases voltage levels as compared to an ordinary cascaded MLI. Thus the devices can switch under line frequency with staircase-type output while maintaining excellent output waveform quality [3]- [5]. To increase control response or further improve output waveform quality, a single-phase MLI can operate with the following two modulation schemes: (1) sinusoidal pulse width modulation (SPWM) for improved output power quality and (2) nearest level modulation (NLM) for improved efficiency and reduced EMI emissions [6], [7].…”

Section: Introductionmentioning

confidence: 99%

Space Vector Techniques for a Binary-Cascaded Multilevel Inverter Operating Under Reduced Common-Mode Voltage With Reduced Commutations

Gutierrez

Baek

Lai

2022

IEEE Open J. Ind. Electron. Soc.

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This paper presents a novel space vector pulse width modulation (SVPWM) for a three-phase binary cascaded multilevel inverter. The SVPWM could become impractical in multilevel inverters (MLIs) because of its increasing complexity with a larger number of levels. The gh coordinate system can ease the digital implementation, but to generate the inverter's abc states from the nearest three vectors (NTVs), iterative computations are required every sampling instant. This paper proposes further reduction of computations by directly generating the abc state with minimum common-mode voltage (CMV) from a gh vector. Subsequently, only one vector among the NTVs is required for implementing the proposed SVPWM. The reduced CMV profile within the NTVs further permits the reduction of commutations by clamping one phase during a sampling period. The presented technique exhibits full dc bus utilization capability and can be implemented in the binary cascaded MLI (BCMLI) and further applied to any M-level MLI. Also, if M is considerably large or if switching losses and electromagnetic interference emissions must be minimized, nearest vector modulation with reduced CMV along with line-frequency operation of high-voltage cells can be implemented to reduce the switching losses. Experiment results of a BCMLI is presented to verify the effectiveness of the proposed technique.INDEX TERMS Common-mode voltage (CMV), multilevel inverter (MLI), nearest vector modulation (NVM), space vector pulse width modulation (SVPWM), switching loss reduction.

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“…Therefore, low power losses and good output quality are obtained for 9L‐HSMC. Some other HMC topologies with reduced power devices have been proposed for high‐voltage applications, such as grid‐connected system [14], high‐frequency link converters [15] and high‐voltage direct current transmission [16]. This work is devoted to explore the overwhelming merits of the HSMCs, in terms of capabilities of voltage balancing and fault tolerance.…”

Section: Introductionmentioning

confidence: 99%

Model predictive control of a hybrid stacked multicell converter with voltage balancing and fault tolerance capability

Sun

Yao

et al. 2021

IET Power Electronics

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Due to the merits of low conduction losses and superior output power quality, a hybrid stacked multicell converter (HSMC) was put forward as a competitive alternative in the medium/low-voltage high-efficiency applications. A nine-level HSMC (9L-HSMC) can be seen as a combination of a five-level SMC (5L-SMC) and two-level half-bridge, and proper modulation and control strategy are essential for the HSMC to obtain the optimal output performance. This work develops a finite control-set model predictive control (MPC) strategy for 9L-HSMC to balance the capacitor voltages and maintain the desired outputs, rendering the absence of the linear regulator and pulse width modulation (PWM) modulator possible. The fault-tolerant operation can also be achieved flexibly when open-circuit faults occur at active bidirectional switches in the 5L-SMC bridge, and the performance is verified by simulations. Finally, experiments under several typical operating conditions are implemented to verify the effectiveness of 9L-HSMC with the developed MPC strategy.

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A Hybrid Binary-Cascaded Multilevel Inverter With Simple Floating-Capacitor-Voltage Control

Cited by 19 publications

References 17 publications

A New Asymmetric Cascaded Multilevel Converter Topology With Reduced Voltage Stress and Number of Switches

A New Asymmetric Cascaded Multilevel Converter Topology With Reduced Voltage Stress and Number of Switches

Space Vector Techniques for a Binary-Cascaded Multilevel Inverter Operating Under Reduced Common-Mode Voltage With Reduced Commutations

Model predictive control of a hybrid stacked multicell converter with voltage balancing and fault tolerance capability

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