A hybrid erasure-coded ECC scheme to improve performance and reliability of solid state drives

Abstract

The high performance and ever-increasing capacity of flash memory has led to the rapid adoption of Solid-State Disks (SSDs) in mass storage systems. In order to increase disk capacity, multi-level cells (MLC) are used in the design of SSDs, but the use of such SSDs in persistent storage systems raise concerns for users due to the low reliability of such disks. In this paper, we present a hybrid erasure-coded (EECC) architecture that incorporates ECC schemes and erasure codes to improve both performance and reliability. As weak error-correction codes have faster decoding speed than complex error correction codes (ECC), we propose the use of weak-ECC at the segment level rather than complex ECC. To compensate the reduced correction ability of weak-ECC, we use an erasure code that is striped across segments rather than pages or blocks. We use a small sized HDD to store parities so that we can leverage parallelism across multiple devices and remove the parity updates from the critical write path. We carry out simulation experiments based on Disksim to demonstrate that our proposed scheme is able reduce the SSD average read-latency by up to 31.23% and along with tolerance from double chip failures, it dramatically reduces the uncorrectable page error rate.

Cost‐effectively improving solid state drive lifetime by hierarchical redundancy and heterogeneous memories

“…The frequent parity writes/updates will affect the write throughput and lifetime endurance of the SSD. To handle those extra writes/updates, solutions 4,5 are proposed.…”

“…Therefore, we deploy the across-chips data redundancy in H2-SSD to reconstruct data strips with uncorrectable bit errors, but not all data on a failed chip, which is different from CR5M 4 and EECC. 5 In other words, we can distribute a portion of strips in the same stripe on one chip, under the assumption those chips rarely fail. More specifically, within one stripe, we need to put the c1 × s data strips on each MLC chip at least, and the s parity strips on the SLC chip, in compensation for the low capacity of the SLC chip, as demonstrated in Figure 3.…”

“…Subedi et al 5 present a hybrid erasure‐coded SSD architecture named EECC which uses a weaken in‐page ECC and deploys an HDD to store parity. The HDD absorbs the parity writes/updates so that both the performance and reliability can be improved.…”

“…As we mentioned in Section 3.1, the SSDs may be destroyed by the uncorrectable bit errors before the chip failures, particularly under a write intensive workload. Therefore, we deploy the across‐chips data redundancy in H2‐SSD to reconstruct data strips with uncorrectable bit errors, but not all data on a failed chip, which is different from CR5M 4 and EECC 5 . In other words, we can distribute a portion of strips in the same stripe on one chip, under the assumption those chips rarely fail.…”

“…However, the remained writes/updates can still significantly affect the write throughput of the SSD and lifetime endurance of the rest chips. EECC 5,6 uses small-size HDD to absorb those extra writes/updates on the parity, but the whole storage subsystem will lose the shock resistance due to that additional HDD. Furthermore, the HDD may become the bottleneck of the overall performance under write intensive workloads.…”