A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

Abstract

We present a hybrid system spanning a fixed-function microarchitecture and a general-purpose microprocessor, designed to amplify the throughput and decrease the power dissipation of collision detection relative to what can be achieved using CPUs or GPUs alone. The primary component is one of the two novel microarchitectures designed to perform the principal elements of broad-phase collision detection. Both microarchitectures consist of pipelines comprising a plurality of memories, which rearrange the input into a format that maximises parallelism and bandwidth. The two microarchitectures are combined with the remainder of the system through an original method for sharing data between a ray tracer and the collision-detection microarchitectures to minimise data structure construction costs. We effectively demonstrate our system using several benchmarks of varying object counts. These benchmarks reveal that, for over one million objects, our design achieves an acceleration of 812× relative to a CPU and an acceleration of 161× relative to a GPU. We also achieve energy efficiencies that enable the mitigation of silicon power-density challenges, while making the design amenable to both mobile and wearable computing devices.

Network Accounting Mode Management in Multimedia Environment on Account of Embedded Microprocessor

“…When the circuit is in a normal working state, the device has a low threshold voltage to increase the driving capability of the digital circuit. In principle, ideally, a dynamic threshold CMOS tube can be realized by connecting the ordinary CMOS tube gate and the substrate together [18]. Take the inverter as an example, as shown in Figure 3:…”

Broadmark: A Testing Framework for Broad‐Phase Collision Detection Algorithms

“…On the multi-core and many-core literature, the number of cores or GPUs and other related costs have been also covered [LLCC13, AGA12, BMPS09, AGA14, CL18, FM17]. Some works aim to use multiple application scenarios [ZE00, LHLK10,SR17] or focus on specific problems, such as the cost of adding/removing objects [TBW09], the behaviour under largely static scenes [TB12], the use of custom hardware [WDM07,WM17] or specific constraints [CL16b,FM17,She14] In addition, physics engines, such as Bullet [Cou18] and PhysX [Nvi19a], are generally not focused on benchmarks, outside their own algorithms and engine versions. Bullet 2 had a broad-phase benchmark, which has been used by some authors as state-of-theart [LHLK10, LLCC13, TBW09]; however, it is no longer available.…”

“…On the multi‐core and many‐core literature, the number of cores or GPUs and other related costs have been also covered [LLCC13, AGA12, BMPS09, AGA14, CL18, FM17]. Some works aim to use multiple application scenarios [ZE00, LHLK10, SR17] or focus on specific problems, such as the cost of adding/removing objects [TBW09], the behaviour under largely static scenes [TB12], the use of custom hardware [WDM07, WM17] or specific constraints [CL16b, FM17, She14]…”