“…chosen the same parameter settings according to the existing designs of [23], [24], [29]- [31], i.e., (n, q) = (256, 256) and (n, q) = (512, 256) ( q = 8), which correspond to the quantum/classic security of 73/84-bits and 140/190-bits, respectively [20]; (iv) for a fair and practical comparison, we set the input/output of the proposed accelerator as serialin/serial-out format; (v) the proposed accelerator also includes the third and fourth polynomials Z and W for operations of both encryption and decryption phases as well as related resources; (vi) for a more general demonstration, we do not use the other available resources on the FPGA devices such as the block RAM (BRAM), etc. ; (vii) we have chosen u = 1, u = 2, u = 4, u = 8, and u = 16 for the proposed KINA, respectively, to showcase the high-speed operational performance under different processing setups; (viii) the obtained area-time complexities, in terms of the number of Lookup table (LUT), maximum frequency (Fmax, MHz), latency cycles, delay (critical-path×latency cycles), area-delay product (ADP), and throughput are all listed in Table II along with those of [23], [24], [29]- [31].…”