A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers

Ju, Hyungyu; Lee, Minjae

doi:10.1109/tvlsi.2020.2986508

Cited by 10 publications

(6 citation statements)

References 21 publications

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“…It can be seen that the pole-zero doublets (-175 & -246 MHz) are large enough in comparison to the unity-gain frequency (ωU) of the GBFC where ωU is around 54 MHz. As illustrated by Ju and Lee [17], if the pole-zero doublet natural frequency is approximately four times the ωU, their destructive effect on the step response can be ignored, which is almost the case here as well. It should be noted that the low-frequency pole and zeros below 1 Hz are omitted in Table 4.…”

Section: Simulation Resultsmentioning

confidence: 64%

Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

Rashtian

Vafapour

2021

IJE

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A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary amplifiers is presented. The proposed auxiliary amplifiers are designed in a way that has proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary amplifiers are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary amplifiers, which keep the output voltage level at the desired. A simple single stage auxiliary amplifier imposes fewer poles and zeroes on the main amplifier compared to more complicated amplifiers where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20 dB while output swing, slew rate, settling time, phase margin, and gainbandwidth retain almost as the same as previous folded cascode design.

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Section: Simulation Resultsmentioning

confidence: 64%

Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

Rashtian

Vafapour

2021

IJE

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“…The SOA, which is the main block of both PGA and TIA circuits, is shown in Figure 9. It is based on a two-stage topology [21] implemented by a fully-differential foldedcascoded operational transconductance amplifier (devices M 0−10 ) followed by a common-source amplifier (transistors M 11−14 ). The first stage delivers high gain bandwidth, while the second stage increases the voltage range of V outp,n to quasi rail-to-rail fulfilling the required trade-off of low power consumption.…”

Section: B Programmable Gain and Transimpedance Amplifiersmentioning

confidence: 99%

“…One way to get rid of it, is using a cascode to block it. Thus, the compensation capacitances C 0−3 are split between the cascode devices of the first stage instead of connecting them between the output and input of the second stage [21]. Sizing these compensation capacitors requires a special trade-off with the above-mentioned compensation resistors R c in the TIA circuit to guarantee the stability and symmetry of the whole chain including multiplexers and sample switches.…”

Section: B Programmable Gain and Transimpedance Amplifiersmentioning

confidence: 99%

Flexible Multi-Channel Analog-Frontend for Ultra-Low Power Environmental Sensing

Jotschke

Reichel

Ossa

et al. 2021

IEEE Open J. Circuits Syst.

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The trend towards ubiquitous electronics drives the development of autonomous hardware components with longer operating times. This work presents a novel ultra-low power analog sensor frontend (AFE) for environmental sensing applications. Relevant operation parameters like resolution (6 to 13 bit), sample rate (1 to 7.5 kS/s), voltage gain (−6 to 12 dB), transimpedance (1.5 to 12 M ), and moving average (1 to 128 taps) are real-time programmable. Four input channels are separately configurable to process voltage, current and potentiometric signals of external or internal sources. The flexible channel-wise configuration enables processing of various signal types and therefore offers a versatile solution for sensors from the Internet-of-Things (IoT) market segment. The AFE integrates switched-capacitor amplifiers, 13 bit, 10 kS/s successive approximation analog-to-digital converter (SAR ADC), bias references, oscillator, digital signal pre-processing and communication in a system-on-chip. A novel sensor power regime supports the flexible read-out of commercial IoT sensors, resulting in excellent power consumption. Fabricated samples in 180 nm technology show an ultra-low power consumption of 8.8 µW. The SAR ADC achieves 10.6 effective bits while consuming 1.8 µW, resulting in a Figure-of-Merit of 116.0 fJ/conv.-step. Measurements with commercial sensors prove the AFE's suitability for an energy-harvester-powered IoT environmental sensor node.

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“…In addition, the miller compensation capacitor will introduce a low frequency zero point [10]. This zero point contributes to a larger phase shift that shifts the phase intersection to the left, greatly reducing the stability of the op-amp.…”

Section: Compensation Circuit Modulementioning

confidence: 99%

A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Bai

2021

Electronics

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Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

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A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers

Cited by 10 publications

References 21 publications

Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

Flexible Multi-Channel Analog-Frontend for Ultra-Low Power Environmental Sensing

A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

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