A hybrid NoC design for cache coherence optimization for chip multiprocessors

Hui, Zhao; Jang, Ohyoung; Ding, Wei; Zhang, Yuanrui; Kandemir, Mahmut; Irwin, M.J.

doi:10.1145/2228360.2228511

Cited by 16 publications

(3 citation statements)

References 21 publications

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“…Some progress has been made in research on hybrid coherence protocols for monolithic multi-core systems. Zhao [10] proposed to dynamically configure short-range snooping buses to form clusters, and use directory protocols between clusters. Li [11] uses Dcache as a small-capacity directory to send coherence requests point-to-point, reducing the number of broadcasts.…”

Section: Related Workmentioning

confidence: 99%

Design of an efficient hybrid cache coherence protocol on chiplet architecture

Wang,

Yu,

Zhuang

2024

Third International Conference on Algorithms, Microchips, and Network Applications (AMNA 2024)

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Section: Related Workmentioning

confidence: 99%

Design of an efficient hybrid cache coherence protocol on chiplet architecture

Wang,

Yu,

Zhuang

2024

Third International Conference on Algorithms, Microchips, and Network Applications (AMNA 2024)

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“…In addition, various approaches for constructing hybrid, regular mesh NoC topologies have been proposed. Zhao et al [10] proposed the use of a HNoC to ease the cache coherency. Manevich et al [11] introduced a bus interconnect, parallel to the regular mesh, to ease the broadcast and the multicast communication.…”

Section: Related Workmentioning

confidence: 99%

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

Todorov

Mueller-Gritschneder

Reinig

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Networks-on-Chip (NoCs) enable cost-efficient and effective communication between the processing elements inside modern systems-on-chip (SoCs). NoCs with regular topologies such as meshes, tori, rings, and trees are well suited for general-purpose many core SoCs. These topologies might prove suboptimal for SoCs with predefined application characteristics and traffic patterns. Such SoCs benefit from application-specific NoC topologies, designed and optimized according to the application characteristics. This paper proposes a synthesis approach for creating hybrid, application-specific NoCs from an input floorplan and a set of use cases, describing the applications running on the SoC. The method considers latency, port count, and link length constraints. It produces hybrid topologies that utilize both NoC routers and shared buses. Furthermore, the proposed approach can insert intermediate relay routers that act as bridges or repeaters and help to reduce the cost further. Finally, the approach creates a deadlock-free routing of the communication flows by either finding deadlock-free paths or by inserting virtual channels. The benefits of the proposed method are demonstrated by comparing it to state-of-the-art approaches on a generic and an industrial SoC examples.

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“…The results show that network latency and energy consumption can be reduced on average by 15% and 27%, respectively when compared to mesh network. Zhao et al [2012] proposed a hybrid interconnect in which buses can share links with a NoC to form a bus-NoC hybrid interconnect. In order to share the links between buses and a NoC, a bus-switch component is added to each router.…”

mentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

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A hybrid NoC design for cache coherence optimization for chip multiprocessors

Cited by 16 publications

References 21 publications

Design of an efficient hybrid cache coherence protocol on chiplet architecture

Design of an efficient hybrid cache coherence protocol on chiplet architecture

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

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