A hybrid software-based self-testing methodology for embedded processor

Abstract

Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test routine development or generation can base on deterministic and random methodology. The deterministic test methodology develops the test program for a pipeline processor using the information abstracted from its architecture model, RTL descriptions, and gate-level net-list for different types of processor circuits. The random test methodology tries to make the pseudo-exhaustive testing possible using random instructions or patterns. The proposed methodology improves coverage for structural faults using both deterministic and random development of the test code. Not only can the deterministic test program test lots of faults using very small code size, but also the random test program can help detect some of the faults that the deterministic test program is difficult to test. We demonstrated the feasibility of the proposed methodology by the achieved fault coverage, test program size, and testing cycle count on a complex pipeline processor core. Comparisons with previous work are also made. Experimental results show its potential as an effective method for practical use.

Adaptive online testing for efficient hard fault detection

“…The advantages of SBST are its low cost, ease of application and extensibility. A variety of proposals have been made for SBST [8], [19], [17] with a considerable success. The latest being [17] that reports up to 97.3% fault coverage.…”

“…A variety of proposals have been made for SBST [8], [19], [17] with a considerable success. The latest being [17] that reports up to 97.3% fault coverage. The test generation algorithms (for SBST and functional testing) can comfortably trade-off the test size with the amount of fault coverage.…”

“…The test generation algorithms (for SBST and functional testing) can comfortably trade-off the test size with the amount of fault coverage. Figure 2 illustrates this trade-off between the amount of fault coverage and the number of software test instructions executed for a ARM9-v4 compatible RISC processor using data from [17]. As seen in the figure, the last few percentages of the coverage require the maximum testing effort (number of test instructions).…”

“…The final equation above also adds bounds to the possible values of the fault coverage, 0 being the minimum and best coverage being the best possible coverage using the test generation technique employed. In this work, we propose the use of software based self test (SBST) to conduct the online testing [17]. The advantage of the software based testing is two fold: 1) no hardware overhead, and 2) the fault coverage level is flexible.…”

“…The advantage of the software based testing is two fold: 1) no hardware overhead, and 2) the fault coverage level is flexible. The proposed methodology in [17] allows generation of test programs to meet different levels of fault coverage. The number of software test instructions are thus tuned on a per core basis to match the fault coverage desired for the same.…”