Adaptive online testing for efficient hard fault detection

Gupta, Shantanu; Ansari, Amin; Feng, Shuguang; Mahlke, Scott

doi:10.1109/iccd.2009.5413132

Cited by 20 publications

(11 citation statements)

References 26 publications

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“…4) Customizable: Unlike prior approaches, approximate circuits provide a common framework that can be customized to provide concurrent error masking for a broad range of failure mechanisms. For example, offline architectural techniques such as periodic testing [8]- [10], [31], lifetime-reliability tracking based on technology parameters [32], and error prediction techniques [20], [21], [24], [25] target only timing errors resulting from gradual slowdown of speed paths, e.g., due to aging mechanisms. On-chip temperature and voltage sensors to predict temperature surges and voltage droops [33] target timing errors due to fast-changing dynamic variability effects such as supply voltage and temperature variations.…”

Section: ) Overhead Versus Error Coverage Tradeoffs: Unlike Tradi-mentioning

confidence: 99%

Low Cost Concurrent Error Masking Using Approximate Logic Circuits

Choudhury

Mohanram

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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With technology scaling, logical errors arising due to single-event upsets and timing errors arising due to dynamic variability effects are increasing in logic circuits. Existing techniques for online resilience to logical and timing errors are limited to detection of errors, and often result in significant performance penalty and high area/power overhead. This paper proposes approximate logic circuits as a design approach for low cost concurrent error masking. An approximate logic circuit predicts the value of the outputs of a given logic circuit for a specified portion of the input space, and can indicate uncertainty about the outputs over the rest of the input space. Using portions of the input space that are most vulnerable to errors as the specified input space, we show that approximate logic circuits can be used to provide low overhead concurrent error masking support for a given logic circuit. We describe efficient algorithms for synthesizing approximate circuits for concurrent error masking of logical and timing errors. Results indicate that concurrent error masking based on approximate logic circuits can mask 88% of targeted logical errors for 34% area overhead and 17% power overhead, 100% timing errors on all timing paths within 10% of the critical path delay for 23% area overhead and 8% power overhead, and 100% timing errors on all timing paths within 20% of the critical path delay for 42% area overhead and 26% power overhead.Index Terms-Concurrent error detection, concurrent error masking, logic synthesis, reliability.

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Section: ) Overhead Versus Error Coverage Tradeoffs: Unlike Tradi-mentioning

confidence: 99%

Low Cost Concurrent Error Masking Using Approximate Logic Circuits

Choudhury

Mohanram

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In contrast, our hybrid solution takes advantage of the low cost of software testing, but improves its coverage through the addition of extra observation points. Gupta, et al [7] suggested tuning the execution of functional tests to the health of the silicon elements within the processor. They estimate hardware health through in-situ oxide breakdown and NBTI sensors spread throughout the silicon, thus increasing chip area by 2.6%.…”

Section: Related Workmentioning

confidence: 99%

Application-Aware diagnosis of runtime hardware faults

Pellegrini¹,

Bertacco²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Current online testing mechanisms focus on testing all components in a microprocessor, including hardware that has not been exercised, and thus have high performance penalties.We propose a hybrid hardware/software online testing solution where components that are heavily utilized by the software application are tested more thoroughly and frequently. Thus, our online testing approach focuses on the processor units that affect application correctness the most, and it achieves high coverage while incurring minimal performance overhead. We also introduce a new metric, Application-Aware Fault Coverage, measuring a test's capability to detect faults that might have corrupted the state or the output of an application. Test coverage is further improved through the insertion of observation points that augment the coverage of the testing system. By evaluating our technique on a Sun OpenSPARC T1, we show that our solution maintains high Application-Aware Fault Coverage while reducing the performance overhead of online testing by more than a factor of 2 when compared to solutions oblivious to application's behavior. Specifically, we found that our solution can achieve 95% fault coverage while maintaining a minimal performance overhead (1.3%) and area impact (0.4%).

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“…One way to do it is to retry the same computation multiple times, and after a certain number of errors in a given interval of time, declare the component as permanently faulty [2].…”

Section: Introductionmentioning

confidence: 99%

Balancing system availability and lifetime with dynamic hidden Markov models

Panerati

Abdi

Beltrame

2014

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Electronic components in space applications are subject to high levels of ionizing and particle radiation. Their lifetime is reduced by the former (especially at high levels of utilization) and transient errors might be caused by the latter. Transient errors can be detected and corrected using memory scrubbing. However, this causes an overhead that reduces both the availability and the lifetime of the system. In this work, we present a mechanism based on dynamic hidden Markov models (D HMMs) that balances availability and lifetime of a multi-resource system by estimating the occurrence of permanent faults amid transient faults, and by dynamically migrating the computation on excess resources when failure occurs. The dynamic nature of the model makes it adaptable to different mission profiles and fault rates. Results show that our model is able to lead systems to their desired lifetime, while keeping availability within the 2% of its ideal value, and it outperforms static rule-based and traditional hidden Markov models (HMMs) approaches.

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Adaptive online testing for efficient hard fault detection

Cited by 20 publications

References 26 publications

Low Cost Concurrent Error Masking Using Approximate Logic Circuits

Low Cost Concurrent Error Masking Using Approximate Logic Circuits

Application-Aware diagnosis of runtime hardware faults

Balancing system availability and lifetime with dynamic hidden Markov models

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