A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

Abstract

This paper presents the simulations and characterizations results of a hybrid Time to Digital Converter (TDC) fabricated in 180 nm standard CMOS. The design combines the traditional Analog Time to Amplitude Converter (TAC) and Digital TDC techniques to obtain a high adjustable time precision. These approach leads to a 3 bits enhancement of the least significant bit resolution (LSB) for the proposed design. The characterization results showed a time precision of 10 ps with an estimated INL of 5.6 ps rms for a 2.5 ns reference period clock and a 32 cells delay line loop.