A Hypervisor for MIPS-Based Architecture Processors - A Case Study in Loongson Processors

Zhou, Rui; Ai, Zhu; Yang, Jiaming; Chen, Yucong; Li, Jun; Zhou, Qing; Li, Kuan‐Ching

doi:10.1109/hpcc.and.euc.2013.124

Cited by 6 publications

(1 citation statement)

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“…Considering the related work as the reliable communication server model [30], SNSP and TMR+1 can be adopted to strengthen the fault-tolerance capability of the model. Additionally, the formal method utilized in this paper is useful to support the verification on the design of hypervisors, as those presented in [31] [32].…”

Section: Discussionmentioning

confidence: 98%

Formal Verification of Fault-Tolerant and Recovery Mechanisms for Safe Node Sequence Protocol

Zhou

Min

et al. 2014

2014 IEEE 28th International Conference on Advanced Information Networking and Applications

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Fault-tolerance has huge impact on embedded safety-critical systems. As technology that assists to the development of such improvement, Safe Node Sequence Protocol (SNSP) is designed to make part of such impact. In this paper, we present a mechanism for fault-tolerance and recovery based on the Safe Node Sequence Protocol (SNSP) to strengthen the system robustness, from which the correctness of a fault-tolerant prototype system is analyzed and verified. In order to verify the correctness of more than thirty failure modes, we have partitioned the complete protocol state machine into several subsystems, followed to the injection of corresponding fault classes into dedicated independent models. Experiments demonstrate that this method effectively reduces the size of overall state space, and verification results indicate that the protocol is able to recover from the fault model in a fault-tolerant system and continue to operate as errors occur.

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Section: Discussionmentioning

confidence: 98%