A L-band gain controllable CMOS LNA

Chen, Fei-hua; Lin, Shen; Xin-Zhong, Duo; Sun, Xiaowei

doi:10.1109/apmc.2009.5384394

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…17(b). Gain control technique [31] is used to digitally control the LNA gain. The measured gain of the LNA and gm-cell can be adjusted from 12 to 46 dB, and the PGA have a measured gain control range of 28 dB.…”

Section: A Receiver Front-end Designmentioning

confidence: 99%

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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This paper presents a Bluetooth low-energy (BLE) transceiver (TRX) achieving ultra-low-power operation for Internet-of-Things (IoT) applications. The proposed TRX utilizes a wide-bandwidth low-power fractional-N digital phase-locked loop (DPLL) as a central component to perform multiple roles: a direct frequency modulator for the transmitter (TX), an analogto-digital converter (ADC) for the receiver (RX), a local oscillator for RX, and a frequency and phase synchronizer for the RX. The DPLL-based single-path downconversion method is adapted to halve the analog baseband circuit to further reduce the power consumption while maintaining a high interference rejection. A DPLL-based ADC with a digital-to-analog converter feedback greatly improves the ADC dynamic range, which improves the RX sensitivity and interference tolerance. By maximally reducing the required radio frequency and analog front-end components in RX, an RX power consumption of 2.3 mW is achieved with a −94 dBm sensitivity. The RX also satisfied all interference requirements with a certain margin. A 5.0-mW TX is achieved when delivering an output power of 0 dBm with a frequency-shift keying error of only 1.89%.

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Section: A Receiver Front-end Designmentioning

confidence: 99%

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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“…A differential circuit is adopted in the proposed LNA in order to reject any noise traveling in substrate [3] [4] and for system match consideration to the following stage. On the other hand, a digital programmable gain control circuit [5] is exploited for gain control in request of the system. Meanwhile problems such as fading effect and reflection from a moving object, causing performance saturation and degradation, can be abated or even solved with gain control circuit [6].…”

Section: Introductionmentioning

confidence: 99%

4.2–4.8 GHz CMOS variable gain LNA for Chinese UWB application

Chen

Lin

et al. 2010

2010 International Conference on Microwave and Millimeter Wave Technology

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The CMOS variable gain low noise amplifier (LNA) presented in this paper is designed for frequency band 4.2 -4.8 GHz ultra-wideband (UWB) application specified in China. Wideband input matching with low noise performance codesign method is shown. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. Fabricated with 0.13-ȝm RF CMOS process, the die size with ESD-pads is 0.9 mm 2 . Drawn 18 mA from 1.2 V DC supply, the LNA exhibits 2.3 dB minimum noise figure, S(1,1) less than -9 dB and S(2,2) less than -10 dB. Maximum and minimum power gain are 28 dB and 16 dB respectively, about 4 dB/step with four gain modes in all. Input 1dB compression point is -10 dBm and input third order intercept point (IIP3) is -2 dBm.

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A High Gain, High IIP3, Perfect Input Matching, Programmable Gain LNA in CMOS Technology

Tajik

TaheriNasab

Sheikhaei

2021

2021 29th Iranian Conference on Electrical Engineering (ICEE)

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A L-band gain controllable CMOS LNA

Cited by 3 publications

References 10 publications

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

4.2–4.8 GHz CMOS variable gain LNA for Chinese UWB application

A High Gain, High IIP3, Perfect Input Matching, Programmable Gain LNA in CMOS Technology

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A L-band gain controllable CMOS LNA

Cited by 3 publications

References 10 publications

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

4.2&#x2013;4.8 GHz CMOS variable gain LNA for Chinese UWB application

A High Gain, High IIP3, Perfect Input Matching, Programmable Gain LNA in CMOS Technology

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4.2–4.8 GHz CMOS variable gain LNA for Chinese UWB application