A leakage current model for SOI based floating body memory that includes the Poole-Frenkel effect

Abstract

The leakage current of SOI based Floating Body Memory (FBM) has been modeled. The model takes into account oxide/SOI interface traps (D it ) and Electric Field Enhanced (EFE) generation of electron hole pairs (EHPs) from trap states via the Poole-Frenkel Effect (PFE). This model has been used to improve the retention

Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission

“…This indicates that Poole-Frenkel Effect is the dominant mechanism of emission of holes from channel to charge trapping layers at low electric fields. 4,5,22 This also explains why large V t shifts are obtained with low program/erase voltages.…”

“…The electric field across the tunnel oxide is calculated using Physics Based TCAD simulations. 3,4,21 With 1 V gate voltage; the electric field across the tunnel oxide is 0.36 MV/cm, and with a 10 V gate voltage; the electric field is 3.6 MV/cm. At an electric field of 1 MV/cm; tunneling over a potential barrier of 1.36 eV is negligible.…”

“…This barrier can be further reduced by the electric field in square-root dependence via the Poole-Frenkel Effect. [3][4][5] In 1938, Frenkel explained the increase of the carriers thermal emission rate in an external electric field by the barrier lowering associated with the Coulomb potential of the carriers: as the applied field increases, the barrier height decreases further, and due to this barrier lowering, the thermal emission rate of charges exponentially increases. 22,24,25 This effect has often been assigned to a donor trap, which is neutral when it contains an electron and is positively charged when the electron is absent so that a Coulombic attraction exists.…”

“…3 At lower electric fields, emission of charges over a reduced potential barrier is possible via Poole-Frenkel Effect (PFE). [3][4][5] Recently, a technology that has been attracting a growing attention is ZnO-based memory devices because they can provide high performance as well as low cost, high environmental stability, and optical transparency. [6][7][8] In parallel, the charge-trapping layer can be engineered to improve the trapping and retention characteristics of the memory, allowing for lower operating voltages and thinner tunnel oxides.…”

TCAD simulation and modeling of impact ionization (II) enhanced thin film c-Si solar cells

“…Chynoweth et al calculated the values of A and b by using an empirical fit from experimental data. In this work, the values for A and b are used from Nayfeh et al [42] and are listed in Table 1 below. Also, we used physics based (PB) TCAD to fit to experimental data.…”