A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

Sudarshan, Chirag; Lappas, Jan; Weis, Christian; Mathew, Deepak M.; Jung, Matthias; Wehn, Norbert

doi:10.1007/978-3-030-27562-4_31

Cited by 10 publications

(6 citation statements)

References 12 publications

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“…In Neo, these buffers are over-provisioned to simplify the initial design of the AXI4 frontend. Despite this, our controller occupies only 6.3 % of the area and 33 % of the beachfront of an existing 65 nm full-pin-count DDR3 controller [25].…”

Section: Silicon Performancementioning

confidence: 99%

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Ottaviano

Benz

Scheffler

et al. 2023

IEEE Trans. Circuits Syst. II

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Power and cost constraints in the internet-ofthings (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous architectures. These designs use energyefficient application-class host processors to coordinate computespecialized multicore accelerators, amortizing the architectural costs of operating system support and external communication. This brief presents Cheshire, a lightweight and modular 64-bit Linux-capable host platform designed for the seamless plug-in of domain-specific accelerators. It features a unique low-pin-count DRAM interface, a last-level cache configurable as scratchpad memory, and a DMA engine enabling efficient data movement to or from accelerators or DRAM. It also provides numerous optional IO peripherals including UART, SPI, I2C, VGA, and GPIOs. Cheshire's synthesizable RTL description, comprising all of its peripherals and its fully digital DRAM interface, is available free and open-source. We implemented and fabricated Cheshire as a silicon demonstrator called Neo in TSMC's 65nm CMOS technology. At 1.2 V, Neo achieves clock frequencies of up to 325 MHz while not exceeding 300 mW in total power on dataintensive computational workloads. Its RPC DRAM interface consumes only 250 pJ/B and incurs only 3.5 kGE in area for its PHY while attaining a peak transfer rate of 750 MB/s at 200 MHz.

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Section: Silicon Performancementioning

confidence: 99%

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Ottaviano

Benz

Scheffler

et al. 2023

IEEE Trans. Circuits Syst. II

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“…The main architectural difference between DRAMSys4.0 and its predecessor is in the simulator's core component, the channel controller. DRAMSys4.0's channel controller architecture is inspired by various advanced RTL DRAM controller implementations (e.g., [19,20,5]). As shown in Fig.…”

Section: Architecture and Functionalitymentioning

confidence: 99%

“…This allows the validation and analysis of hardware with the framework's provided tools (see Section 2.3) without any manual translation to a higher abstraction level. As an example, the Verilog description of the DDR3 channel controller presented in [5] was auto-translated into an equivalent SystemC RTL model by the Verilator tool 5 . To convert TLM transports from arbiter and DRAM devices into associated RTL signals (including a clock signal, which is not present in DRAMSys) and vice versa, a special transactor module is wrapped around the RTL design.…”

Section: Embedding Of Rtl Controllersmentioning

confidence: 99%

“…Cycle-accurate DRAM simulation models (left side) provide full temporal accuracy for reliable investigations, but usually take a lot more time to execute. RTL descriptions of real DRAM controllers [5] can be simulated using a Discrete Event Simulation (DES) kernel. State-of-the-art cycle-accurate DRAM simulators, namely DRAMSim2 [6], DRAMsim3 [7], Ramulator [8] and DrSim [9], avoid the overhead of a DES kernel and use a simple loop to represent clock cycles.…”

Section: Introductionmentioning

confidence: 99%

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DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses

Steiner

Jung

Prado

et al. 2022

Int J Parallel Prog

Self Cite

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The simulation of Dynamic Random Access Memories (DRAMs) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM subsystem models often become a bottleneck for the overall simulation speed. A promising alternative are simulators based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest and most extensive open-source cycle-accurate DRAM simulation framework. DRAMSys4.0 includes a novel software architecture that enables a fast adaption to different hardware controller implementations and new JEDEC standards. In addition, it already supports the latest standards DDR5 and LPDDR5. We explain how to apply optimization techniques for an increased simulation speed while maintaining full temporal accuracy. Furthermore, we demonstrate the simulator’s accuracy and analysis tools with two application examples. Finally, we provide a detailed investigation and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.

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“…Moreover, if the implementation of the controller is added, the size is expected to be approximately seven times. [14] provided a thesis implemented on the controller, excluding PHY, in the memory system. The memory type was not known exactly, but when compared to this paper, a size of approximately four times larger can be determined.…”

Section: Asic Chipmentioning

confidence: 99%

Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Kim¹,

Park

Cho

2021

Electronics

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In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

Cited by 10 publications

References 12 publications

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses

Study on the Implementation of a Simple and Effective Memory System for an AI Chip

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