A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

Abstract

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

“…Although assigning higher threshold voltage to the circuit gates decreases the power consumption [25], we did consider the improvements achieved by the proposed DVth on power consumption. The reason behind this is that, the goal of the proposed framework is to improve the circuit lifetime reliability (and not the power consumption).…”

“…In [24], an analytical methodology for accurate modeling of the correlation between Process, Voltage and Temperature variations (PVT) and BTI-induced aging is presented. In [25], a machine learning approach is proposed to predict the NBTI degradation of the circuit paths. A fast, accurate, and versatile PV-and aging-aware delay model for generic cell libraries called AADAM is presented in [26].…”

“…Based on transistor-level SPICE simulations, the delay degradation of each library cell is characterized under a set of variability and aging factors. It is notable that PV-and aging analysis methods suffer from limitations: some of the previous works only consider NBTI effect (and neglect PBTI) [14], [15], [21]- [25] or some others just focused on one challenge (either PV or aging effect) [8]- [11] leading to inaccurate analysis results. Moreover, most of the other works, which consider both PV and aging effects, use the old reactiondiffusion theory to consider NBTI and PBTI effects on circuits [7] [16].…”

Logical Resolving-Based Methodology for Efficient Reliability Analysis

“…The above two steps constitute the cell-level aging simulation, which is indispensable for aging timing analysis [ 1 ]. Based on the cell-level aging simulation, it can be extended to the aging-aware STA for digital circuits, whose typical practices include aging-aware std-cell libraries characterization [ 18 ] and distinguish the potential critical paths [ 19 ]. So we will verify both two practices combined with the proposed methods.…”