A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers

Passamani, Antonio; Ponton, D.; Knoblinger, G.; Bevilacqua, Andrea

doi:10.1109/prime.2014.6872748

Cited by 17 publications

(4 citation statements)

References 6 publications

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“…The common technique to reduce loss is to increase their widths to reduce r on . However, careful optimization of the MOSFETs' width is required as it linearly increases the parasitic capacitance C p making the dynamic losses predominant [7] (Fig. 2).…”

Section: Drain Efficiency Modelmentioning

confidence: 99%

Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI

Tochou

Cathelin

Frappé

et al. 2022

IEEE Trans. Circuits Syst. II

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The Switched-Capacitor Power Amplifier (SCPA) has become a key enabler for modern wireless communication because of its high efficiency, high linearity, and high integrability. This paper discusses the impact of the extended Forward Body-Biasing (FBB) feature in 28 nm FD-SOI technology on Ultra-Low Voltage (ULV) SCPA. A new model of the Drain Efficiency (DE) and System Efficiency (SE) including body-biasing and drivers power consumption is introduced and validated with SpectreRF simulations. FBB on the SCPA improves by up to 14 % and 67 % the SE and transistors area, respectively, compared to a nominally body-biased SCPA under 0.5 V supply voltage at 2.4 GHz, while improving linearity and enhancing PVT variations.

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Section: Drain Efficiency Modelmentioning

confidence: 99%

Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI

Tochou

Cathelin

Frappé

et al. 2022

IEEE Trans. Circuits Syst. II

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“…First, a dynamic loss in the CMOS inverter stage as described in [40] results from simultaneous switching of PMOS and NMOS transistors as well as due to parasitic input and output capacitances. The average power dissipated by the inverter P switch calculates to…”

Section: B Rf-dac Drain Efficiencymentioning

confidence: 99%

“…with n I and n Q describing the quantized codewords acting on the unitary-weighted RF-DAC cells. The technology parameter β is independent from the CMOS inverter size but shows a linear dependency on rise-and fall-times of the switching and operating frequency [40]. Second, due to the switched capacitive voltage divider as shown in Fig.…”

Section: B Rf-dac Drain Efficiencymentioning

confidence: 99%

A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

Buckel

Preyler

Klinkan

et al. 2018

IEEE Trans. Circuits Syst. I

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A novel digital-intensive hybrid transmitter (TX) architecture is presented, combining conventional inphase and quadrature (I/Q) with constrained phase modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF clock and adjusted I/Q components. By incorporating phase modulation the quadrature component is kept small while the inphase component approaches the complex signal envelope. Compared to a digital-quadrature TX architecture this results in a significantly reduced average and peak RF-DAC cell utilization. Therefore, the RF-DAC can be operated in less backoff at higher average output power and drain efficiency. The phase modulation is constrained in order to relax the phase modulators system requirements. Compared to a digital polar TX architecture utilizing an RF digital phase-locked loop with two-point phase modulation, this results in reduced frequency modulation and digital-controlled oscillator tuning range requirements. In addition, the design effort is further shifted from analog to digital domain in order to better exploit the benefits of CMOS technology scaling. Index Terms-Wireless communication, digital polar transmitter, digital quadrature transmitter, hybrid polar-I/Q transmitter, phase modulation, quadrature modulation, RF digital-to-analog converter (RF-DAC), RF digital power amplifier (RF-DPA), RF digital phase-locked loop (RF-DPLL). I. INTRODUCTION W IRELESS transceivers for multi-band, multi-standard mobile handset applications operating in the sub-6 GHz range are usually implemented in ultra-deep

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“…The SCPA efficiency analysis is presented in detail in [9] and [15]. The MN provides the correct load impedance for the maximum efficiency, contributes to the impedance matching with the next stage and provides a bandpass characteristic in order to filter the square wave V o .…”

Section: Digital Power Amplifier Based Transmittermentioning

confidence: 99%

Integration solutions for reconfigurable multi-standard wireless transceivers

Kale

Batistell

Popuri

et al. 2018

Elektrotech. Inftech.

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This article presents an overview of modern integration concepts for receiver, transmitter and duplexer architectures. Based on innovative design techniques, a system-in-package integrated RF transceiver architecture is proposed as a low-cost low-power alternative to traditional multi-standard transceivers. The proposed transceiver architecture unites advantages of a sub-sampling receiver with tunable low noise amplifier (LNA), a high-efficiency digital power amplifier and an integrated duplexer with on-package passive components in order to fulfill the more and more stringent requirements for wireless systems. In addition to the transceiver architecture, measurement results of building blocks are presented. A LNA circuit implemented in 65 nm CMOS technology provides a continuously tunable-gain (3-23 dB) and a tunable frequency band (4.5 GHz-5.5 GHz) with noise figure of 2 dB and IIP 3 of −6.5 dBm at the highest gain. A high Q-factor, on-package transformer, implemented in a core-less 3-metal layer system-in-package substrate, presents a coupling factor of 0.6 and a Q-factor of approximately 30. This provides a low-cost, high-performance alternative solution to integrated matching networks and duplexers. IntroductionModern wireless transceivers require multi-band and multi-standard operation, which leads to complex, bulky and power hungry implementations. An architecture for state-of-the-art multi-standard transceiver is shown in Fig. 1, where several transmitter (TX) and receiver (RX) chains are required in order to fulfill specifications for wireless standards.With the evolution of wireless systems, even more communication standards are being proposed while maintaining backward compatibility, therefore, cost and complexity of RF transceivers tend to increase. For high-performance communication standards, external off-chip components with optimized performance such as duplexer filter and power amplifier (PA), are necessary to satisfy ever-growing standard requirements. On the contrary, for low-performance battery operated applications such as Internet of things (IoT), lowpower and low-cost implementations are desired.This article presents a set of innovative design concepts, for receivers, transmitters and system-in-package (SiP) integration, which provides reconfigurability, wide frequency operation, higher power efficiency and low-cost. Based on the presented concepts, an RF transceiver architecture shown in Fig. 2 is proposed. The RX chain is based on a tunable active-balun LNA and a sub-sampling down-

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A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers

Cited by 17 publications

References 6 publications

Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI

Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI

A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

Integration solutions for reconfigurable multi-standard wireless transceivers

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