A linear programming formulation for security-aware gate sizing

Abstract

Differential power analysis (DPA) has been shown to be the dominant type of side-channel attacks that significantly jeopardize the security in integrated circuits. It has been shown that the data, the functional unit operations as well as the internal micro-architectures can be detected through current and power analysis. Subsequently, different CMOS logic styles have been proposed in the literature for performing computations in such a manner that the current and power signatures can be concealed through reduction of the variance in transient power dissipation. In this work, we propose a gate sizing formulation based on traditional static CMOS standard cells that improves the security of the circuits while maintaining low overheads in terms of area, power and delay. The proposed algorithm considers all disjoint paths from primary inputs to the primary outputs, performing gate sizing with the objective of balancing the switched path capacitances among the various paths making it difficult to extract power or current signatures through current or power profiling. Further, we show that the path based security aware gate sizing formulation is NP-complete and propose a greedy approximation algorithm based on linear programming. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks and the experimental results indicate a reduction of the variance of transient dynamic power by about 40% with very low overhead in terms of delay, area and power.

Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present

“…There are at least three methodologies for security aware sizing. Bhattacharya et al [34] formulate the sizing problem considering the switching activity of the transistors and the capacitances of each interconnection node of the circuit. In 2009 [35], Lin and Burleson developed an iterative algorithm to resize the higher capacitances gates of the circuit.…”

Dynamic security domain scaling on embedded symmetric multiprocessors

“…The goal of data security is to protect the integrity and privacy of confidential data from attacks. Much work on data security, such as XOM [Lie et al 2000]; AEGIS [Suh et al 2005]; SENSS [Zhang et al 2005]; split mask countermeasure [Gebotys 2006]; WDDL [Tiri and Verbauwhede 2006]; security-aware gate sizing [Bhattacharya and Ranganathan 2008]; and TPM [TCG 2006]; protects private keys.…”

Gate sizing using Geometric Programming

“…The most widely known is the logical effort method [2], which provides fast heuristics or design guidelines for solving the gate-sizing problem approximately. In [3] and [4], Linear Programming is used. NonLinear Programming is used in [5] and [6].…”