A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

“…4. As input signal changes from 0.1 V to 1.1 V, the change of parasitic capacitance in [29] and [31] are higher 33%, and 11%, respectively. The change of parasitic capacitance is small in [30], however, with three auxiliary switches, the total parasitic capacitance is increased.…”

“…In structure [30], three auxiliary switches are used and unnecessary parasitic capacitance of sampling switch will increase obviously. The total parasitic capacitance is also depressed compared with [31], in which, the parasitic capacitance and compensation capacitance are in parallel. Consequently, the equivalent parasitic capacitance of the proposed switch is reduced obviously.…”

“…That means the threshold voltage of sampling switch is reduced and the onimpedance of sampling switch will decrease. A small Cc is used to bias the PW instead of additional switches in [30] and [31], low on-impedance is achieved with small parasitic capacitance in the proposed structure.…”

“…The parasitic capacitance of sampling switches in 40-nm CMOS process are imported to MATLAB. Simulation results of the relationship between total source/drain to substrate parasitic capacitance (CB) of sampling switch and Vin in [29,30,31] and the proposed technique are exhibited in Fig. 4.…”

“…But three auxiliary switches are needed and more parasitic capacitances are imported. A linearityimproved sampling switch with parasitic capacitance compensation technique is exhibited in [31] without the triplewell process, the change of parasitic capacitance is reduced, but the total parasitic capacitance will increase after compensation and the sampling speed is restrained. This Letter proposes a substrate floating technique for high linearity sampling switch of SAR ADC, the change of parasitic capacitance and total parasitic capacitance of sampling switch are both reduced.…”