A Locating Method for Reliability-Critical Gates with a Parallel-Structured Genetic Algorithm

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

“…10,11 To shorten the product development cycle and improve market competitiveness, analyzing and estimating the impact of soft errors on circuit reliability at an early stage of circuit design is a growing need. [12][13][14][15] Historically, soft errors have been tackled in the context of memory cells because of the large chip area devoted to caches and the higher vulnerability of SRAM cells in comparison with combinational logic circuits. 16 In the last few years, their negative effect on memory has been kept under control by using protection mechanisms, such as error-correcting codes.…”

“…10,[19][20][21] They are often used to quickly and efficiently calculate the reliability of combinational circuits and identify the reliability-critical gates. 15,21 However, they are not conducive to measuring the reliability of the functional blocks that make up the circuits, 22,23 which makes them unfavorable for the implementation of selective hardening operations based on functional blocks. Therefore, the propagation of soft errors in logic circuits was analyzed at register transfer level (RTL) by various researchers using fault simulation 24,25 and formal verification methods.…”

“…Because they are widely used in medical, military, and flight control systems, paying attention to the reliability of the circuits is the need of the hour 10,11 . To shorten the product development cycle and improve market competitiveness, analyzing and estimating the impact of soft errors on circuit reliability at an early stage of circuit design is a growing need 12–15 . Historically, soft errors have been tackled in the context of memory cells because of the large chip area devoted to caches and the higher vulnerability of SRAM cells in comparison with combinational logic circuits 16 .…”

“…Several approaches have been developed to analyze soft error propagation at the gate level 10,19–21 . They are often used to quickly and efficiently calculate the reliability of combinational circuits and identify the reliability‐critical gates 15,21 . However, they are not conducive to measuring the reliability of the functional blocks that make up the circuits, 22,23 which makes them unfavorable for the implementation of selective hardening operations based on functional blocks.…”