A Low-Complexity Edward-Curve Point Multiplication Architecture

Sajid, Asher; Rashid, Muhammad; Imran, Malik; Jafri, Atif Raza

doi:10.3390/electronics10091080

Cited by 15 publications

(37 citation statements)

References 32 publications

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“…This multiplier executes and offers low memory and low power. Sajid et al [10] proposed the reduction of complexity at the instruction level for unified PD and PA operation. The design uses the execution of multiple functions in a single instruction format.…”

Section: Literature Reviewmentioning

confidence: 99%

“…The most time-consuming and dominant function in ECC is elliptic curve scalar multiplication (ECSM) and it is presented as Q=kP; where Q is another point on the elliptic curve, P is defined as a base point on an elliptic curve, and k is a scalar. The primary goal of the PM is to multiply the private key and fundamental point on the elliptic curve to determine the public key [10].…”

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confidence: 99%

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High speed elliptic curve cryptography architecture for NIST recommended Galois field

2022

IJATEE

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Nowadays there is an intense increase in data communications over wireless and wired based networks. Everyday lakhs of transactions happen over the World Wide Web. These transactions have significant data that required confidentiality, validity, and authenticity in data transactions on the openended network [1]. Modern security requires the use of cryptographic algorithms because every transaction is associated with a cyberattack. To provide higher security, both asymmetric and symmetric cryptographic algorithms are operated in data transmission for information exchange [2]. Asymmetric algorithms are commonly employed in secure communication to exchange and manage keys, whereas symmetric cryptographic algorithms are utilised for high-throughput secure data exchange [3].

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Section: Literature Reviewmentioning

confidence: 99%

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confidence: 99%

High speed elliptic curve cryptography architecture for NIST recommended Galois field

2022

IJATEE

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“…Similarly, P is the initial point on the defined curve. To perform a PM operation, there are several algorithms, i.e., Double and Add (recently employed in [27]), Montgomery (utilized in [14,19,21,24]), Lopez Dahab (implemented in [18]), and many more. A comprehensive comparison over hardware implementations of various PM algorithms is presented in [2].…”

Section: Background For Pm Computationmentioning

confidence: 99%

“…Therefore, multiple inversion methods can be considered. However, the Itoh-Tsujii inversion algorithm is more frequently utilized as it requires only the multiplications and square operations for the computation [14,18,19,21,22,24,27]. Based on this consideration, we used similar hardware resources of our employed multiplier and squarer architectures to perform the required inversion operations to implement Algorithm 1.…”

Section: Adder Squarer and Multipliermentioning

confidence: 99%

A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

et al. 2021

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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

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“…It can potentially increase the resistance to SPA attacks [13,14]. In this context, Binary Edwards curves [15], which are known for their ability to resist side-channel attacks, are being increasingly used in various high-security applications. Compared to Binary Huff curves [16] and Hessian curves [17], Binary Edwards curves are not only faster and more secure, but also have a smaller key size and require less computational resources, making them ideal for constrained environments [6].…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Approach for Efficient and Secure Point Multiplication on Binary Edwards Curves

et al. 2023

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The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient hardware resource utilization for the point multiplication process over GF(2m). This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for GF(2233) on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources.

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A Low-Complexity Edward-Curve Point Multiplication Architecture

Cited by 15 publications

References 32 publications

High speed elliptic curve cryptography architecture for NIST recommended Galois field

High speed elliptic curve cryptography architecture for NIST recommended Galois field

A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

A Hybrid Approach for Efficient and Secure Point Multiplication on Binary Edwards Curves

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