A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors

Falcón, Ayose; Ramírez, Alex; Valero, V.

doi:10.1109/hpca.2004.10003

Cited by 9 publications

(6 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The performance of BAT scheme is evaluated using Simplescalar3.0 tool set [4] on 10 SPEC2000 CPU benchmarks. Firstly, since the instruction fetch delay is the performance bottleneck of modern superscalar CPU [2], we study the data flow between Level-1 instruction cache (L1-icache) and instruction buffer unit. Similarly to [2], a Harvard architecture is adopted.…”

Section: Discussionmentioning

confidence: 99%

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission

Yan

Liu

2008

IEICE Transactions on Electronics

View full text Add to dashboard Cite

Crosstalk delay within an on-chip bus can induces a severe transmission performance penalty. Bus-grouping Asynchronous Transmission (BAT) scheme is proposed to mitigate the performance degradation. Furthermore, considering the distinct spatial locality of transition distribution on some types of buses, we use the locality to optimize the BAT. In terms of the implementation, we propose the Differential Counter Cluster (DCC) synchronous mechanism to synchronize the data transmission, and the Delay Active Shielding (DAS) to protect some critical signals from crosstalk and optimize the routing area overhead. The BAT is scalable with the variation of bus width with little extra implementation complexity. The effectiveness of BAT is evaluated by focusing on the on-chip buses of a superscalar microprocessor simulator using the SPEC CPU2000 benchmarks. When applied to a 64-bit on-chip instruction bus, the BAT scheme, compared with the conservative approach, Codec and Variable Cycle Transmission (DYN) approaches, improves performance by 55 + %, 10 + %, 30 + %, respectively, at the expense of 13% routing area overhead.

show abstract

Section: Discussionmentioning

confidence: 99%

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission

Yan

Liu

2008

IEICE Transactions on Electronics

View full text Add to dashboard Cite

show abstract

“…This situation is more acute for fetch mechanisms that fetch instructions from up to two threads each cycle. If we use high performance fetch mechanisms like [8], that provides as high performance as previous ones, this situation is reduced.…”

Section: Related Workmentioning

confidence: 99%

Implicit vs. explicit resource allocation in SMT processors

Cazorla¹,

Knijnenburg

Sakellariou

et al. 2004

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

Self Cite

View full text Add to dashboard Cite

show abstract

“…A modification of the stream fetch engine for SMT processors was evaluated in HPCA'04 [16], showing relevant impact on the choice of the fetch policy to be used when fetching from a single thread on each cycle. A stream predictor capable of issuing multiple predictions per cycle was shown in ISHP'05 [17]. And a mechanism to store decoded instructions (like the Pentium4 trace cache) in the standard instruction cache was presented in PACT'06 [18] (archive version published in IEEE ToC'09 [19]).…”

Section: Related and Follow-up Workmentioning

confidence: 99%

Author retrospective for software trace cache

Ramírez

Falcón²,

Santana

et al. 2014

25th Anniversary International Conference on Supercomputing Anniversary Volume -

View full text Add to dashboard Cite

In superscalar processors, capable of issuing and executing multiple instructions per cycle, fetch performance represents an upper bound to the overall processor performance. Unless there is some form of instruction re-use mechanism, you cannot execute instructions faster than you can fetch them.Instruction Level Parallelism, represented by wide issue out of order superscalar processors, was the trending topic during the end of the 90's and early 2000's. It is indeed the most promising way to continue improving processor performance in a way that does not impact application development, unlike current multicore architectures which require parallelizing the applications (a process that is still far from being automated in the general case). Given that the typical basic block size in SPEC integer benchmarks is 4-6 instructions, fetch performance was limited to those same 4-6 instructions per cycle, making 8-wide and 16-wide superscalar processors impractical. It became imperative to find mechanisms to fetch more than 8 instructions per cycle, and that meant fetching more than one basic block per cycle. The Trace Cache [2] [3][4] quickly established itself as the state of the art in high performance instruction fetch. The trace cache relies on a trace building mechanism that dynamically reorders the control flow of the program, and stores the dynamic instruction sequences in sequential storage, increasing fetch width.However, it is a complex hardware structure that adds not only another cache memory to the on-chip storage hierarchy, but also requires a branch predictor capable of issuing multiple predictions per cycle to index the contents of the trace cache, and distinguish between multiple dynamic sequences of instructions.The Software Trace Cache is a compiler transformation, or a postcompilation binary optimization, that extends the seminar work of Pettis and Hansen PLDI'90 to perform the reordering of the dynamic instruction stream into sequential memory locations using profile information from previous executions. The major advantage compared to the trace cache, is that it is a software optimization, and does not require additional hardware to capture the dynamic instruction stream, nor additional memories to store them. Instructions are still captured in the regular instruction cache. The major disadvantage is that it can only capture one of the dynamic instruction sequences to store it sequentially. Any other control flow will result in taken branches, and interruptions of the fetch stream.Our results show that fetch width using STC was competitive with that obtained with the hardware TC, and was applicable to a wide range of superscalar architectures, because it does not require hardware changes to enable fetching from multiple basic blocks in a single cycle, even if only one branch prediction can be issued. Any front-end architecture built on a BTB that ignores branches as long as they are not taken, will automatically treat such branches as NOP instructions in terms of fetch [5].This was only the...

show abstract

A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors

Abstract: Simultaneous Multithreading (SMT) is an architectural

Cited by 9 publications

References 34 publications

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission

Implicit vs. explicit resource allocation in SMT processors

Author retrospective for software trace cache

Contact Info

Product

Resources

About