A low-cost high-speed self-checking carry select adder with multiple-fault detection

Valinataj, Mojtaba; Mohammadnezhad, Abbas; Nurmi, Jari

doi:10.1016/j.mejo.2018.08.014

Cited by 16 publications

(8 citation statements)

References 17 publications

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“…There exist various full adder (FA) designs in the literature such as [17,18]. However, the concept of self-checking FA was initially introduced by Akbar and Lee [1], and later was used in other researches [3,5]. This concept is based on the fact that when all three inputs of a FA, i.e.…”

Section: Self-checking Full Addermentioning

confidence: 99%

“…Among the processing units, the adders are very important due to their usage as one of the main functions. Thus, there exist various reported designs to address error detection in the adders such as those reported in literature [1][2][3][4][5] in addition to the multipliers [6,7] even in the reversible logic domain. The carry select adder (CSeA) is one of the fast adders utilized in the processing systems.…”

Section: Introductionmentioning

confidence: 99%

“…The carry select adder (CSeA) is one of the fast adders utilized in the processing systems. Many researches have been conducted in recent years to reduce the cost and enhance the performance and reliability of the CSeAs [1,5,[8][9][10]. The self-checking CSeA design is discussed in the researches of Akbar and Lee [1,8].…”

Section: Introductionmentioning

confidence: 99%

“…The self-checking CSeA design is discussed in the researches of Akbar and Lee [1,8]. However, Valinataj et al proposed a method to achieve multiple fault/error detection is proposed for the CSeAs [5]. Moreover, some improvements in delay, *Corresponding Author Email: m.valinataj@nit.ac.ir (M. Valinataj) energy or power and the silicon area were reported in literature [9,10].…”

Section: Introductionmentioning

confidence: 99%

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An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder

Valinataj

2021

IJE

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In this paper, an enhanced self-checking carry select adder (CSeA) architecture is introduced. However, we first show that the carry select adder design presented by akbar and lee does not have the self-checking property in all of its parts in spite of the stated claim. Then, we present a corrected design with the selfchecking property that requires more overheads. In addition, we reveal some mistakes in reporting the transistor count of the proposed design in the literature in different sizes, and correct them which again leads to more transistor count and overhead. At the end, due to the fact that the performance of a CSeA depends on its grouping structure, the area overheads of different CSeAs including the corrected designs and the best of previous self-checking designs will be evaluated with respect to the same-size and different-size grouping structures. These evaluations show the comparison of different CSeAs, more appropriate compared to the previous evaluations.

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Section: Self-checking Full Addermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder

Valinataj

2021

IJE

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“…Computations are mainly performed in the arithmetic and logic unit (ALU) of the processors so designing them fault-tolerant is very important. In this context, applying redundancy to various aspects of the system is applicable but the resulting overhead should be studied precisely based on the requirements of embedded systems [14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

FT-EALU: Fault Tolerant Arithmetic and Logic Unit for Critical Embedded and Real time Systems

Abdi¹,

Shahoveisi²

2022

Preprint

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In this paper, a fault-tolerant approach to mitigate transient and permanent faults of arithmetic and logic operations of embedded processors called FT-EALU is proposed. In this method, each operation is replicated in time and the derived final results are voted to generate the final output. To consider the effect of permanent faults, replicating identical operations in time is not sufficient, and diversifying the operands is required. To this aim in FT-EALU, we consider three distinct versions of input data and apply the target operation to them serially in time. To avoid high time overhead, we employ simple operators such as shift and swap to make an appropriate diversion in input data. Our proposed fault tolerance approach passes the replicated and diverse results to a novel weighted voter that is designed based on the reward/punishment strategy. For each version of execution, based on the proposed weighting approach a corresponding weight according to its correction capability confronting several faulty scenarios is defined. This weight defines the reliability of the result of each version of execution and determines its effect on the final result. The final result is generated bit by bit based on the weight of each execution and its computed result. These weights are determined statically through a design-time learning scheme according to applying several types of faults on various data bits. Based on the capability of execution versions on mitigating the permanent faults, positive or negative scores are assigned to them. These scores are integrated for several cases and normalized to derive the appropriate weight of each execution at bit level. These weights are employed as the predefined values in our proposed weighted voting approach as the trust factor of each bit of results to improve system reliability. Several experiments are performed to show the efficiency of our proposed approach and based on them, FT-EALU is capable of correcting about 84.93% and 69.71% of permanent injected faults on single and double bits of input data.

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Low Power and Highly Reliable 8-Bit Carry Select Adder

Pritty

Jhamb

2020

Lecture Notes in Electrical Engineering

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A low-cost high-speed self-checking carry select adder with multiple-fault detection

Cited by 16 publications

References 17 publications

An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder

An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder

FT-EALU: Fault Tolerant Arithmetic and Logic Unit for Critical Embedded and Real time Systems

Low Power and Highly Reliable 8-Bit Carry Select Adder

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