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For continuous real-time monitoring of personal health, wearable devices are indispensable. The constraints of cost, power consumption, and limited device dimensions are the critical issues which need to be handled carefully while designing these battery-powered devices. The wearables employ high-end processors dedicated for complex signal processing. The core of every digital signal processor is its data path. The arithmetic units like adders constitute the core of data path and addressing unit. This work proposes a novel low-complexity asynchronous pipelined adder. The proposed design guarantees great savings in power and latency, which makes it a suitable candidate for low-power highspeed sophisticated wearables. The proposed design consumes a minimum power of 33.46 µW and offers a minimum propagation delay of 0.04 ns in comparison to state-of-art adders such as ripple carry adder (RCA), carry look ahead adder (CLA), and carry select adder (CSA). Thus, an area-delay-power efficient adder design guarantees high-end performance for wearables.

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