Efficient adders for assistive devices

Jhamb, Mansi; Gitanjali, .

doi:10.1016/j.jestch.2016.09.007

Cited by 11 publications

(3 citation statements)

References 11 publications

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“…Jhamb Mansi et al 2016 proposed dynamic logic gates for wide fan in gates as a discretionary decision for expansive memory and rapid applications. This is because it is located near standard Complementary Metal-Oxide-Semiconductor (CMOS) logical gates [1]. Domino logic circuits can achieve high speed, thanks to its low noise edge compared to standard CMOS logic.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Prasath¹,

Shankar²

2023

Intelligent Automation &Amp; Soft Computing

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Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor (CMOS)-based Very Large-Scale Integration (VLSI) circuit designs. Positive Channel Metal Oxide Semiconductor (PMOS) has been replaced by Negative Channel Metal Oxide Semiconductor (NMOS) in recent years, with low dimension-switching changes in order to shape the mirror of voltage comparator. NMOS is used to reduce stacking leakage as well as total exchange. Domino Logic Circuit is a powerful and versatile digital programmer that gained popularity in recent years. In this study regarding Adaptive Sub Threshold Voltage Level Control Problem, the researchers intend to solve the contention issues, reduce power dissipation, and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control (ASVLC)-based domino circuit. The efficiency and effectiveness of the domino circuit are demonstrated through simulation results. The suggested system makes use of high-speed broad fan-gate circuits, occupies minimum space, and consumes meagre amount of power. The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V, frequency of 100 MHz, and an operating temperature of 27°C with 64 input OR gates. As per the simulation results, the suggested Domino Gate reduced the power dissipation by 17.58 percent and improved the noise immunity by 1.21 times in comparison with standard domino logic circuits.

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Section: Introductionmentioning

confidence: 99%

Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Prasath¹,

Shankar²

2023

Intelligent Automation &Amp; Soft Computing

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“…The challenge here is to design an adder which shows less propagation delay, lower utilization of power and occupying less chip area for such applications. Asynchronous designs occupy less power as compared to synchronous counter parts due to absence of global clock [10]. This work proposes an asynchronous pipelined adder and its performance has been compared with state-of-art adders [11][12][13][14].The pipelining is discussed in section 2.…”

Section: Introductionmentioning

confidence: 99%

High Speed PS0 Micro-Pipelined Adder

Jhamb*,

Pudi*,

Vats

2020

IJRTE

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For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.

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“…A large conglomeration of algorithms has been implemented for binary addition [7][8][9]. Asynchronous circuit design is inherently low-power due to absence of a global synchronizing signal [10]. The design is robust across all process-voltage-temperature (PVT) corners.…”

Section: Introductionmentioning

confidence: 99%

Pipelined adders for ultralow-power wearables

Jhamb¹,

Dhall²,

Verma³

et al. 2019

Turk J Elec Eng & Comp Sci

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For continuous real-time monitoring of personal health, wearable devices are indispensable. The constraints of cost, power consumption, and limited device dimensions are the critical issues which need to be handled carefully while designing these battery-powered devices. The wearables employ high-end processors dedicated for complex signal processing. The core of every digital signal processor is its data path. The arithmetic units like adders constitute the core of data path and addressing unit. This work proposes a novel low-complexity asynchronous pipelined adder. The proposed design guarantees great savings in power and latency, which makes it a suitable candidate for low-power highspeed sophisticated wearables. The proposed design consumes a minimum power of 33.46 µW and offers a minimum propagation delay of 0.04 ns in comparison to state-of-art adders such as ripple carry adder (RCA), carry look ahead adder (CLA), and carry select adder (CSA). Thus, an area-delay-power efficient adder design guarantees high-end performance for wearables.

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Efficient adders for assistive devices

Cited by 11 publications

References 11 publications

Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

High Speed PS0 Micro-Pipelined Adder

Pipelined adders for ultralow-power wearables

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