Ultra low power design of multi-valued logic circuit for binary interfaces

Jhamb, Mansi; Mohan, Ratnesh

doi:10.1016/j.jksuci.2021.01.010

Cited by 7 publications

(4 citation statements)

References 21 publications

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“…The last two beats of the padding are used to identify the length of the valid data in the plaintext message. 15 The plaintext message is then grouped by 512 bits.…”

Section: A Sha-1 Algorithm Modelmentioning

confidence: 99%

DMA controller design based on SHA-1 dual channel improvement algorithm

Wang,

He,

Shi

2023

AIP Advances

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In order to make direct memory access (DMA) high-speed transmission while ensuring the security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from the algorithm model and hardware architecture level by adopting the methods of data synchronization preprocessing and multi-block multi-output, and a dual-channel design with instant data comparison and data error correction functions adapted to high-speed DMA is achieved. The simulation results show that the maximum clock frequency of the DMA controller is 120 MHz and the throughput rate is up to 3.8 Gbps. The improved comparison channel can output the message summary at an interval of 0.56 μs, whereas the traditional algorithm needs to wait five times as long as the data handling time. The error correction channel also implements multi-block output and error block indexing. The results show that the improved dual-channel design based on the SHA algorithm can be highly adapted to DMA controllers and has good application prospects.

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“…The last two beats of the padding are used to identify the length of the valid data in the plaintext message. 15 The plaintext message is then grouped by 512 bits.…”

Section: A Sha-1 Algorithm Modelmentioning

confidence: 99%

DMA controller design based on SHA-1 dual channel improvement algorithm

Wang,

He,

Shi

2023

AIP Advances

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“…The primary constraint in the binary logic is the existence of only two states (‘0’ and ‘ V DD ’), which leads to introducing more input bits to implement complicated functions, thereby, increasing chip size and power/energy consumption. Therefore, sooner than it is expected binary logic‐based computing machines face an enormous challenge due to the severe thermal and reliability problems 3 . Multiple‐valued logic (MVL) circuits are a more generalized form of binary logic and have more than two‐valued logic to reduce interconnections, chip area, and power/energy consumption.…”

Section: Introductionmentioning

confidence: 99%

“…the severe thermal and reliability problems. 3 Multiple-valued logic (MVL) circuits are a more generalized form of binary logic and have more than two-valued logic to reduce interconnections, chip area, and power/energy consumption. It is an obvious advantage to process a signal in more than two levels from the information content point of view.…”

mentioning

confidence: 99%

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

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SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

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“…However, our study has allowed us to consider that this gap can be bridged through simplification. Indeed, one can build a machine that performs its task effectively and efficiently from the point of view of consumption if it uses a base greater than two [14], [15].…”

Section: Introductionmentioning

confidence: 99%

A New Approach for Designing of Computer Architectures Using Multi-Value Logic

Simonetta¹,

Paoletti²,

Muratore³

2021

International Journal on Advanced Science, Engineering and Information Technology

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In the last decade, we have seen how Moore's law has lost its validity because it has reached the physical limit of miniaturization of components and the problem of thermal dissipation increasing with the chip's clock frequency. For this reason, multi-core architectures were born, and quantum computing is being looked at as a possible solution for more computing power. The aim of this article is to demonstrate the possibility to realize computer architectures using multi-value logic. The objective is reached when we are able to translate any MVL function into the corresponding MVL circuit. The method proposed is completely independent of the basis adopted in the MVL domain and the physical quantity used to represent or transfer the domain values. Thus, this approach provides a new theoretical and practical context for applying new technologies or polymorphic materials, which can represent multiple values. In order to give concreteness to the analyzed theoretical aspects, we will represent a case study based on a classical combinational circuit, the summing circuit using LTspice® XVII (© Analog Device Corporation) as simulation environment has been carried out. The results show that it is possible to build MVL combinatorial circuits, although there are limitations because the proposed solution is just a proof of concept. The method can also be successfully applied to sequential MVL circuits, which are not the subject of the present article.

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Ultra low power design of multi-valued logic circuit for binary interfaces

Cited by 7 publications

References 21 publications

DMA controller design based on SHA-1 dual channel improvement algorithm

DMA controller design based on SHA-1 dual channel improvement algorithm

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

A New Approach for Designing of Computer Architectures Using Multi-Value Logic

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