Design, implementation and performance comparison of multiplier topologies in power-delay space

Jhamb, Mansi; Garima, .; Lohani, Himanshu

doi:10.1016/j.jestch.2015.08.006

Cited by 39 publications

(14 citation statements)

References 9 publications

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“…It is drawbacks is drop in threshold voltage, static power consumption and delay increases with long pass-transistor chains. The Double Pass-transistor Logic (DPL) approach is the modi ed of CPL approach, it has some advantages as well-balanced input capacitance No drop voltage, no need buffers, full swing and low power, its main problems are large area and inverters need [29][30][31][32].…”

Section: Low Power Vlsi Approaches Overviewmentioning

confidence: 99%

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

El‐Bendary

El-Badry

2021

Preprint

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Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (7, 4) and (11, 7) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No.Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

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Section: Low Power Vlsi Approaches Overviewmentioning

confidence: 99%

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

El‐Bendary

El-Badry

2021

Preprint

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“…From the point of view of designing an ASIC-chip that implements fast linear convolution, you should pay attention to the fact that the hardwired multiplier is a very resource-intensive arithmetic unit. The multiplier is also the most energy-intensive arithmetic unit, occupying a large crystal area [26] and dissipating a lot of energy [27]. Reducing the number of multipliers is especially important in the design of specialized fully parallel ASIC-based processors because minimizing the number of necessary multipliers reduces power dissipation and lowers the cost implementation of the entire system being implemented.…”

Section: Implementation Complexitymentioning

confidence: 99%

Some Algorithms for Computing Short-Length Linear Convolution

Cariow

Papliński

2020

Electronics

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In this article, we propose a set of efficient algorithmic solutions for computing short linear convolutions focused on hardware implementation in VLSI. We consider convolutions for sequences of length N= 2, 3, 4, 5, 6, 7, and 8. Hardwired units that implement these algorithms can be used as building blocks when designing VLSI -based accelerators for more complex data processing systems. The proposed algorithms are focused on fully parallel hardware implementation, but compared to the naive approach to fully parallel hardware implementation, they require from 25% to about 60% less, depending on the length N and hardware multipliers. Since the multiplier takes up a much larger area on the chip than the adder and consumes more power, the proposed algorithms are resource-efficient and energy-efficient in terms of their hardware implementation.

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“…Speed and power consumption are the two main aspects considered while designing a system in the field of communication [1]. The multipliers (more specifically the adders) which form the major part of these systems affect its speed [2].…”

Section: Introductionmentioning

confidence: 99%

Pipelined vedic multiplier with manifold adder complexity levels

Eshack¹,

Krishnakumar²

2020

IJECE

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Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is noticed that as complexity of adders in the multipliers reduce, the systems show improved speed and least hardware utilization. The architecture designed using 2 x 2 – bit pipelined Vedic multiplier is, then, compared with existing Vedic multipliers and conventional multipliers and shows least delay.

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Design, implementation and performance comparison of multiplier topologies in power-delay space

Cited by 39 publications

References 9 publications

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

Some Algorithms for Computing Short-Length Linear Convolution

Pipelined vedic multiplier with manifold adder complexity levels

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