A low cost reliable architecture for S-Boxes in AES processors

Abstract

This paper presents a fault-tolerant architecture for AES processors in order to mitigate the reliability issues introduced by the continued shrinking of CMOS technology. We concentrate on the faults occurring on S-Boxes which consume the largest hardware in AES processor. This hybrid solution combines time redundancy and hardware redundancy strategies for masking all single transient and permanent faults. By exploiting the inherent redundancy of AES processor with parallel implementation, the proposed solution limits the area overhead and overcomes many popular fault-tolerant techniques such as Triple Modular Redundancy approach and Triple Temporal Redundancy approaches.

Practical fault resilient hardware implementations of AES

“…This approach can also detect all single bit faults and 99.996% of random faults, it should be noted that the single-byte fault coverage of this approach is ∼50%. Between correction strategies, HT-CFTA has the lowest throughput degradation (54%), and after that, CFTA achieves 69.5%, which is almost the same as that for the fault-resilient approach in [22].…”

“…banking systems, smart cards, automotive vehicles, and health care monitoring [27]. Table 6 compares the area overhead, throughput degradation, and fault coverage of the CFTA, HT-CFTA, and R-CFTA schemes with those of other related fault-resilient designs [7][8][9]22].The comparison results show that two related fault-resilient schemes that are based on time redundancy, i.e. [7][8], posed lower area overhead and throughput degradation on the original AES than the proposed approaches.…”

“…Table 6 compares the area overhead, throughput degradation, and fault coverage of the CFTA, HT‐CFTA, and R‐CFTA schemes with those of other related fault‐resilient designs [7–9, 22]. The comparison results show that two related fault‐resilient schemes that are based on time redundancy, i.e.…”

“…Several research studies have been developed on parallel AES hardware implementation targeting fault resilient, e.g. [2,13,[22][23][24]. In [13], a detection approach based on partial duplication, with ∼25% area overhead and negligible throughput degradation, is proposed for the parallel implementation of AES.…”

“…Several correction approaches for AES have been proposed so far, based on various types of redundancies. For instance, a fault-correction technique based on the hamming code has been proposed in [21] and also a hybrid redundancy approach for AES S-Box was given in [22].…”