SummaryElliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest‐Shamir‐Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex‐7 FPGA platform over 224‐bit and 256‐bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal‐oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area‐delay product and high throughput value in both FPGA and ASIC when compared with other designs.

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In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte-Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

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Neural networks are mimetic with biological neuron which are employed on digital computers. These networks are designed with CMOS technology using 0.45[Formula: see text][Formula: see text]m in cadence virtuoso. The scaling of CMOS limits parameters like power consumption, area and parallelism. To overcome the limitations, a nanoscale, nonvolatile Memristor device is used to design the synapses. The proposed network is designed for neuron synapse networks implemented with a memristor device. This network is compared with neuron linked with CMOS synapse. The proposed network has low power consumption, high spike frequency, and low delay value. The spike frequency of Memristor synapse increases by 65.51% when compared with the existing CMOS synapse and power consumption is reduced to 52.79%. The delay is reduced to 0.294[Formula: see text][Formula: see text]s. The simulation results are carried using Specter.