High-performance ECC processor architecture design for IoT security applications

Kudithi, Thirumalesu; Sakthivel, R.

doi:10.1007/s11227-018-02740-2

Cited by 43 publications

(26 citation statements)

References 25 publications

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“…Among these the AT and throughput values of Ref. [1]- [2] and [6] are approximately equal with our design.…”

Section: Results and Performance Analysismentioning

confidence: 67%

“…So, we used throughput rate parameter and area-delay product (AT) parameter for comparison purposes. Table II, gives the simulated results and performance from various papers presented by Hossain et al [2], Liu et al [3], Lee et al [4], Vliegen [5], Ghosh et al [6], McIvor et al [7], Daly et al [8] and Kudithi et al [9]. We can observe that the results from Hossain et al [2] and Kudithi [9] are better in terms of area and computation time when compared with other literature results.…”

Section: Results and Performance Analysismentioning

confidence: 78%

“…Mrabet et al [5] Virtex-E 1390 41.00    † Normalized value, AT = 1/0.00215932655 = 463.10735, where A: area (slices) and T: time (s). Moreover, Kudithi [6] design has decreased in the throughput of 22% when compared with our FSM method. The development of modular inversion in Virtex-II and Virtex-E are listed out and these designs are obsolete now.…”

Section: Results and Performance Analysismentioning

confidence: 92%

See 2 more Smart Citations

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

Kudithi¹,

Sakthivel²

2019

IJITEE

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The modular inversion operation is an essential hardware design for computing speed when we use it in cryptography applications. Through this work, we present a FSM based design methodology to achieve speed, area and high-performance modular binary inversion algorithm over 256-bit prime field. The proposed architecture implemented using Xilinx Virtex-7 FPGA device, it achieves 37% reduction in area-delay product and 15% and 16% of improvement in speed and throughput respectively, when compared with existing designs. Also, ASIC based implementation is done using TSMC 65nm CMOS technology, the synthesis results achieved the maximum operating clock frequency is 833 MHz and throughput of 626Mbps, which makes it suitable for speed-critical cryptoapplications.

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“…Among these the AT and throughput values of Ref. [1]- [2] and [6] are approximately equal with our design.…”

Section: Results and Performance Analysismentioning

confidence: 67%

Section: Results and Performance Analysismentioning

confidence: 78%

Section: Results and Performance Analysismentioning

confidence: 92%

See 1 more Smart Citation

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

Kudithi¹,

Sakthivel²

2019

IJITEE

Self Cite

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“…The technique proposed to implement multiplicative inverse design attained an operating frequency of 137.22 MHz with resource utilization of only 900 slices over GF (256). In [37], [39] works implemented using virtex-7 device showcased higher speed but with increased area consumption. Other designs [38], [40], [41] synthesized using virtex-5 and virtex-2 FPGA had lower performance in terms of both slices and frequency of execution.…”

Section: Implementation Resultsmentioning

confidence: 99%

Efficient hardware prototype of ECDSA modules for blockchain applications

Devika

Bhakthavatchalu

2021

TELKOMNIKA

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This paper concentrates on the hardware implementation of efficient and reconfigurable elliptic curve digital signature algorithm (ECDSA) that is suitable for verifying transactions in Blockchain related applications. Despite ECDSA architecture being computationally expensive, the usage of a dedicated standalone circuit enables speedy execution of arithmetic operations. The prototype put forth supports N-bit elliptic curve cryptography (ECC) group operations, signature generation and verification over a prime field for any elliptic curve. The research proposes new hardware framework for modular multiplication and modular multiplicative inverse which is adopted for group operations involved in ECDSA. Every hardware design offered are simulated using modelsim register transfer logic (RTL) simulator. Field programmable gate array (FPGA) implementation of var-ious modules within ECDSA circuit is compared with equivalent existing techniques that is both hardware and software based to highlight the superiority of the suggested work. The results showcased prove that the designs implemented are both area and speed efficient with faster execution and less resource utilization while maintaining the same level of security. The suggested ECDSA structure could replace the software equivalent of digital signatures in hardware blockchain to thwart software attacks and to provide better data protection.

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“…In [30], the parallel architecture depends on using the Montgomery ladder for field GF 2 191 but with Karatsuba-Ofman for the polynomial multiplier and Extended Euclidian Algorithm (EEA) for the inversion. However, the work in [31] presented an ECCP architecture design for IoT securityusing the Montgomery ladder algorithm running sequentially. All previous works results appeared in Fig.2.…”

Section: Related Workmentioning

confidence: 99%

Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices

Khadra

Abdulrahman

Ismail

2020

Menoufia Journal of Electronic Engineering Research

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An Elliptic Curve Crypto-Processor (ECCP) is a favorite public-key cryptosystem due to its small key size and its high security arithmetic unit. It is applied in constrained devices which often run on batteries and have limited processing, storage capabilities and low power. This research work presents an effective ECCP architecture for security in IoT and embedded devices. A finite field polynomial multiplier takes the most implementation effort of an ECCP because it is the most consuming operation for time and area. So, the objective is to implement the main operation of Point Multiplication (PM) = using FPGA. The aim is to obtain the optimal registers number for an area optimization of ECCP architecture. Moreover, it proposes a time optimization of ECCP based on the liveness analysis and exploiting forward paths. Also, a comparison between sequential and parallel hardware design of PM based on Montgomery ladder algorithm is provided. The developed ECCP design is implemented over Galois Fields GF (2 163) and GF (2 409) on Xilinx Integrated Synthesizes Environment (ISE) Virtex 6 FPGA. In case of GF (2 163), this work achieved an area saving that uses 2083 Flip Flops (FFs), 40876 Lookup Tables (LUTs) and 19824 occupied slices. The execution time is 1.963 s runs at a frequency of 369.529 MHz and consumes 5237.00 mW. In case of GF (2 409), this work achieved an area saving that uses 8129 Flip Flops (FFs), 42300 Lookup Tables (LUTs) and 18807 occupied slices. The execution time is 29 s runs at a frequency of 253.770 MHz and consumes 2 W. The obtained results are highly comparable with other state-of-the-art crypto-processor designs. The developed ECCP is applied as a case study of a cryptography protocol in ATMs.

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High-performance ECC processor architecture design for IoT security applications

Cited by 43 publications

References 25 publications

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

Efficient hardware prototype of ECDSA modules for blockchain applications

Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices

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