A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation

Zhang, Ziji; He, Yajuan

doi:10.1109/tcsii.2017.2709801

Cited by 34 publications

(37 citation statements)

References 11 publications

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“…The DT scheme reduces HW costs; however, its operation accuracy is very low. To address the PT and DT issues, numerous TEC-based methods have been proposed for FWBMs [21]- [32] or even fixed-width Baugh-Wooley array multipliers [17]- [20]. For a general FWBM design realizing the TEC scheme, Fig.…”

Section: Fwbm Tec Schemes (Literature Review)mentioning

confidence: 99%

“…Numerous FWBM designs with TEC schemes have been reported [21]- [32]. Generally, these studies obtained the bias value (i.e., B (k) in (7)) using computer simulation [21]- [25] and probability estimation [25]- [32] methods. For the simulation-based methods [21]- [25], in [21], the bias terms were derived using simulation findings, followed by the Karnaugh map simplification.…”

Section: Fwbm Tec Schemes (Literature Review)mentioning

confidence: 99%

“…The authors of [25] also presented a probabilistic analysis, together with their simulation-based works. Moreover, the probability estimation methods [27]- [32] derived the closed forms of the bias function based on the expected value or conditional probability for PP terms. In [27], the expected values for two groups of TPminor (with or without n0, …, nQ−1 terms) are individually estimated and combined to obtain the probabilistic estimation bias when w = 1.…”

Section: Fwbm Tec Schemes (Literature Review)mentioning

confidence: 99%

“…For MAC units using Booth multipliers, the aforementioned approach can be employed using a fixed-width Booth multiplier (FWBM), which allows an L-bit  L-bit Booth multiplier to truncate the L least significant bits (LSBs) and preserve the L most significant bits (MSBs) at its output for a full numerical range. To reduce HW costs for the operations associated with the truncated L-bit LSBs of a full-width product, the concept of truncation error compensation (TEC) has been proposed for fixed-width multiplier designs [17]- [32]. TEC uses an estimated bias function to compensate for the truncation error associated with reduced HW costs.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

Tang

Han

2020

IEEE Access

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This paper presents a multiply-accumulate (MAC) unit that enables a dual-mode truncation error compensation (TEC) scheme based on a fixed-width Booth multiplier (FWBM) for convolutional neural network (CNN) inference operations. The proposed tailored TEC schemes of Modes 1 and 2 can achieve high MAC accuracy for a general or rectified linear unit-based CNN model with general (Mode 1) or positive/zero (Mode 2) input patterns. By pre-calculating the pre-known CNN model coefficients, the proposed dual-mode TEC scheme can be realized using minimal partial product operations with high hardware efficiency using a software-hardware codesign approach. Further, a reconfigurable architecture of the resultant MAC unit is presented to realize the proposed dual-mode TEC scheme. By evaluating the accuracy for 9-N and 25-N MAC operations (N denotes the number of times MAC is performed), a MAC operation using the proposed TEC scheme can achieve the highest accuracy for Modes 1 and 2, relative to contrast samples that directly employ the FWBM with a conventional TEC function. The hardware performances of 9-N and 25-N MAC units are also evaluated using the TSMC 40-nm standard cell library. Compared with the contrast TEC-enabled designs, the proposed MAC unit exhibits higher hardware efficiency in terms of area, delay, and power consumption and achieves a minimum reduction of more than 40% in both area-delay-error and power-delay-error products. Moreover, the resultant 9-N and 25-N MAC units are verified using a system-on-chip field-programmable gate array platform to test a CNN model for handwritten digit classification.

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Section: Fwbm Tec Schemes (Literature Review)mentioning

confidence: 99%

Section: Fwbm Tec Schemes (Literature Review)mentioning

confidence: 99%

Section: Fwbm Tec Schemes (Literature Review)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

Tang

Han

2020

IEEE Access

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“…Nevertheless, this correction constant produces a non-zero component. Finally, Zhang et al [29] designed an approximate multiplier by dividing the partial product matrix into two parts: the main part (MP) that is accurately accumulated, and the truncated part (TP), that is further partitioned into TP major and TP minor , with the latter being produced through a probabilistic approach. Dynamic Scaling: in this category, the aggressiveness of the approximations is defined either by the system or according to the inputs.…”

Section: Prior Artmentioning

confidence: 99%

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers

Leon

Asimakopoulos

Xydis

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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Approximate computing appears as an emerging and promising solution for energy-efficient system designs, exploiting the inherent error-tolerant nature of various applications. In this paper, targeting multiplication circuits, i.e., the energy-hungry counterpart of hardware accelerators, an extensive exploration of the errorś energy trade-off, when combining arithmetic-level approximation techniques, is performed for the first time. Arithmetic-aware approximations deliver significant energy reductions, while allowing to control the error values with discipline by setting accordingly a configuration parameter. Inspired from the promising results of prior works with one configuration parameter, we propose 5 hybrid design families for approximate and energy-friendly hardware multipliers, consisting of two independent parameters to tune the approximation levels. Interestingly, the resolution of the state-ofthe-art Pareto diagram is improved, giving the flexibility to achieve better energy gains for a specific error constraint imposed by the system. Moreover, we outperform prior works in the field of approximate multipliers by up to 60% energy reduction, and thus, we define the new Pareto front.

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Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers

Chen

Lai

et al. 2021

Circuit Theory & Apps

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Summary The great demand of high‐performance fixed‐width two's‐complement modified Booth multipliers (FWBM) arises because of the wide applications of approximate computing. In this paper, a row‐based direct‐mapping (RDM) method for designing error estimators in FWBM is proposed. The proposed closed form is derived from probability summation of each entire row to avoid the long setup time of exhaustive simulations. Consequently, a simple and systematic procedure by the Karnaugh map can be utilized to design low‐error and hardware‐efficient compensation circuits for various widths of FWBMs. By checking the leading column of the truncation part, the extendable design principle can be easily applied to different lengths and different columns inspected. We use Synopsys Design Compiler and TSMC 90 nm standard cell library to synthesize the register transfer language (RTL) design of our proposed estimators. In addition, the RDM is synthesized using the Xilinx Vivado tool with Xilinx Kintex‐7 XC7K325T‐2FFG900C FPGA. Results of software simulation, hardware synthesis, and implementation experiment validate the high accuracy, hardware saving, and power efficiency of the proposed RDM estimators.

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A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation

Cited by 34 publications

References 11 publications

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers

Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers

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