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This paper introduces a simple, yet controllable scheme to pick up a single 13 nm Au nanoparticle (Au-NP) using the tip of an atomic force microscope (AFM) probe through the application of electrical biases between the tip and the Au-NP. Transmission electron microscope (TEM) images were acquired to verify that a single Au-NP was attached to the AFM probe. We postulate that the mechanism underlying the ability to manipulate individual Au-NPs at the apex of the AFM probe tip is Coulomb interaction induced by tip bias. The AFM tip with the attached Au-NP was then used to study the interaction between a single quantum dot (QD) and the Au-NP. The blinking behavior of single colloidal CdSe/ZnS core/ shell QD was significantly suppressed with the approach of the 13 nm Au-NP attached to the AFM tip.

This paper presents a novel method for the attachment of a 1.8-nm Au nanoparticle (Au-NP) to the tip of an atomic force microscopy (AFM) probe through the application of a current-limited bias voltage. The resulting probe is capable of picking up individual objects at the sub-4-nm scale. We also discuss the mechanisms involved in the attachment of the Au-NP to the very apex of an AFM probe tip. The Au-NP-modified AFM tips were used to pick up individual 4-nm quantum dots (QDs) using a chemically functionalized method. Single QD blinking was reduced considerably on the Au-NP-modified AFM tip. The resulting AFM tips present an excellent platform for the manipulation of single protein molecules in the study of single protein-protein interactions.

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This study presents a fast Fourier transform (FFT) kernel for multistandard applications, which employ multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM). The proposed design uses a mixed-radix, mixed-multipath delay-feedback (MRM2DF) structure, which enables 4/5/6-stream 64/128-point FFT. This approach allows the effective usage of guard intervals (GI) in conjunction with a novel resource-sharing scheme to improve area efficiency. An area-reduced constant multiplication unit and sorting buffer with minimal memory size further reduced an area overhead. A test chip was designed using UMC 90-nm technology, and was evaluated through post-layout simulation. The proposed design outperformed previous works in terms of the throughput per area.