A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA

Shin, Jongshin; Seo, Il-Won; Kim, Ji Young; Yang, Seung-Hee; Kim, Chiwon; Pak, Jaehyun; Kim, Hyun‐Goo; Kwak, Myoungbo; Hong, Ghy Boong

doi:10.1109/cicc.2006.320969

Cited by 16 publications

(8 citation statements)

References 6 publications

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“…Several techniques have been proposed, including direct modulation of the VCO [9], [10], two-point modulation [11] and the use of fractional-N modulation [12]- [22]. The use of a delay locked loop followed by a phase selector is investigated in [23].…”

Section: Introductionmentioning

confidence: 99%

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

De¹,

Romani

Petra³

et al. 2010

IEEE J. Solid-State Circuits

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Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile.We present the implementation of an all-digital spread spectrum clock generator. The circuit is realized by using a design flow completely based on standard cells and is able to perform clock spreading with an arbitrary modulation profile and a modulation frequency up to 5 MHz. The circuit uses two digitally controlled delay lines driven by a digital modulator to synthesize the output waveform. A replica delay line is employed in a real-time measurement circuit to track process, voltage and temperature variations.A chip has been implemented in a 65 nm CMOS technology. The chip is able to generate signals up to 1.27 GHz. The measured peak level reduction of the clock spectrum, at 750 MHz output frequency, is 20.5 dB with a 6% modulation depth. The power dissipation is 44 mW @ 1.27 GHz.Index Terms-Clock synthesis, digitally controlled delay line, EMI reduction, spread-spectrum clock generator (SSCG).

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Section: Introductionmentioning

confidence: 99%

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

De¹,

Romani

Petra³

et al. 2010

IEEE J. Solid-State Circuits

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“…In order to reduce the EMI, several methods are presented such as device shielding, EMI filter and spread-spectrum clocking (SSC) [1]- [5]. For example, the shielding to protect electronic device is the effective way to the EMI reduction.…”

Section: Introductionmentioning

confidence: 99%

A 3 GHz spread-spectrum clock generator with a self-calibration technique

Chang

Hung

Lin

et al. 2011

2011 IEEE 9th International New Circuits and Systems Conference

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A spread-spectrum clock generator (SSCG) with self-calibration circuit (SCC) is presented in this paper. By the use of self-calibration scheme, exploited the proposed linear circuit and a SCC, the gain of Kvco can be effectively reduced and the jitter performance is improved. Moreover, the proposed architecture provides an alternative technique for low Kvco instead of the commonly used methods for voltage-control oscillator (VCO) calibration. The SCC-based SSCG ensures phase locking under the process, voltage and temperature (PVT) variations. For spread-spectrum clocking, the digital MASH delta-sigma modulator and a 33-kHz triangular addressor is used. The proposed SSCG generates an output clock of 3 GHz and approximate 5000-ppm down spreading with a triangular-modulated shape. The SSCG has been designed in TSMC 0.18 μm CMOS technology. Operating at a 3-GHz clock rate, the peak-to-peak jitter of non spread-spectrum is 3.85 ps. The electromagnetic interference (EMI) reduction is larger than 20 dB with a triangular-modulated frequency of 3 2.985 GHz. I. INTRODUCTIONAs the speed of computer operation increases, the highspeed system clock also accompanies large amounts of electromagnetic interference (EMI). In order to reduce the EMI, several methods are presented such as device shielding, EMI filter and spread-spectrum clocking (SSC) [1]- [5]. For example, the shielding to protect electronic device is the effective way to the EMI reduction. However, the method of shielding is not an economic way due to the area cost. Thus, a mechanism of SSC to adjust clock signal by frequency modulation is acknowledged as the effective and economic way. Accordingly, a spread-spectrum clock generator (SSCG) based on SSC can effectively spread out the power of the clock for the EMI issue.There are many methods to design a high-speed oscillator in phase-locked loop (PLL). The use of the LC tank voltagecontrolled oscillator (VCO) is popular, whereas the output frequency range is narrow. In addition, the narrow operating frequency range and large area cost leads to the difficulty for chip integration. A ring-based oscillator is the alternative architecture for clock oscillation. However, owing to process, voltage and temperature (PVT) variations, the large Kvco gain is designed to cover the required frequency. The high

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“…The first type of SSCG is using the method which directly adds the spread spectrum modulation on low-pass filter (LPF) [3]. The second type of SSCG is to use DSM phase modulation or phase compensation to spread spectrum [2], [4], [5]. The third type SSCG is to change the divider number of the fractional-N frequency synthesizer [1], [6].…”

Section: Introductionmentioning

confidence: 99%

A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator

Huang

Tseng

et al. 2008

2008 IEEE International SOC Conference

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This work presents a new architecture of spread-spectrum clock generator providing 1.5-Gbit/s, 3-Gbit/s and 6-Gibt/s SATA compatible specifications. A two-stage delta-sigma modulator is proposed to simplify the hardware and to overcome the nonlinearity issue of triangular control voltage induced by supply voltage, process and temperature variations. The peak energy of the output clock spectrum is reduced by 17.3dB at 6-GHz. The chip is designed in a 0.18-um CMOS process with an area of 0.57×0.45 mm 2 . The power consumption is 106 mW at a power supply of 1.8-V.

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A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA

Cited by 16 publications

References 6 publications

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

A 3 GHz spread-spectrum clock generator with a self-calibration technique

A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator

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