2016 IEEE International Nanoelectronics Conference (INEC) 2016
DOI: 10.1109/inec.2016.7589361
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A low miller capacitance VDMOS with shield gate and oxide trench

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Cited by 5 publications
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“…First, C dep decreases with the expansion of the depletion region of the bulk region. Second, the grounded central implant region under the gate screens the gate-to-drain capacitive coupling [19] . CIMOSFET has low C RSS despite having shallow depletion regions in high V DS (Fig.…”
Section: Capacitance and Gate Charge Characteristicsmentioning
confidence: 99%
“…First, C dep decreases with the expansion of the depletion region of the bulk region. Second, the grounded central implant region under the gate screens the gate-to-drain capacitive coupling [19] . CIMOSFET has low C RSS despite having shallow depletion regions in high V DS (Fig.…”
Section: Capacitance and Gate Charge Characteristicsmentioning
confidence: 99%
“…The PN junction formed between the P-base and N-drain is used to support high voltages by utilizing a lightly doped drift region. In this paper, based on VDMOS (Vertical-Diffused MOSFET) [11][12][13] and UMOS (U-shaped groove MOSFET) [14,15] structures, the novel VD-GCBFET (figure 1(a)) and U-GCBFET (figure 1(b)) structures are proposed and investigated for the first time by applying the base-gate short contact instead of the original base-source short contact. The simplified circuit diagram is equivalent to that the MOSFET in parallel with the composite BJT, as shown in figure 1(c).…”
Section: Device Structurementioning
confidence: 99%