A low noise, 1.28&amp;#x00B5;A quiescent regulator with broadband high PSR for micropower sensors

Ong, G. T.; Chan, P.K.

doi:10.1109/iscas.2012.6271901

Cited by 6 publications

(11 citation statements)

References 5 publications

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“…9 shows the variation of GM and PM from zero load current to full load current at CL= 0 pF, 50 pF, and 100 pF. As can be seen, the obtained minimum PM is about 46 degree and the minimum GM is about 6 dB.…”

mentioning

confidence: 87%

“…These problems will cause the regulator to operate unreliably which contributes potential errors in the subsequent system. Finally, the LDO regulator may suffer from poor PSR performance due to lower loop gain and poor frequency response [9]. These raise the motivation of this project for the investigation of a sub-1 µA level output-capacitorless LDO regulator that addresses the above stated problems.…”

Section: Motivationsmentioning

confidence: 99%

“…Among the blocks, the power management unit (PMU) are delivering the necessary power to the respective blocks. The front-end sensing devices together with built-in electronic interfaces often require a quality power supply with features of less noise and ripple [9]. The PMUs in each case supports the important devices like sensors, microprocessors and so forth, as shown in As seen from Figure 1.2, the primary power supply which is generated by the energy harvesting power source presents noise as well as ripple.…”

Section: Motivationsmentioning

confidence: 99%

“…Exemplary ultra-low power regulator dedicated to energy harvesting based sensor system for environmental monitoring application[9] …”

mentioning

confidence: 99%

“…9. illustrates the variation of gm1 in the differential stage during the negative load current step from 100 mA to 0 A.…”

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confidence: 99%

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A CMOS low dropout regulator for internet of things

Jiang¹

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With the growing demand of portable devices or the emergence of Internet-of-Things (IoT) applications, the push for small-size and ultra-low-power Low Dropout (LDO) Regulators becomes the key design agenda. Unfortunately, when approaching ultralow power, the transient performance metrics of the regulator are often significantly reduced. Moreover, the parasitic poles of regulator's devices, which are located at low frequencies, can lead to the instability issue. As such, these undesirable effects pose the serious design challenges in the context of ultra-low quiescent power design constraints. To tackle the stated problems, an ultra-low quiescent power capacitorless LDO regulator is proposed with employment of the transistor degeneration frequency compensation (TDFC) in the adaptive frequency compensation scheme. It can deliver a full loading current range from 0 to 100 mA and provide a 1 V output voltage from a 1.2 V power supply at a capacitive load of 100 pF whilst consuming only 407 nA for the entire regulator architecture. The total on-chip capacitance is 6.5 pF. On top of that, a distributed overshoot reduction (DOVSR) topology is also proposed to tackle the overshoot reduction problem under ultra-low quiescent circuit design. By incorporating the TDFC scheme and the feedforward biasing design, this results in reduced settling time and overshoot voltage with respect to that of the conventional circuit technique.

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mentioning

confidence: 87%

Section: Motivationsmentioning

confidence: 99%

Section: Motivationsmentioning

confidence: 99%

“…Exemplary ultra-low power regulator dedicated to energy harvesting based sensor system for environmental monitoring application[9] …”

mentioning

confidence: 99%

“…9. illustrates the variation of gm1 in the differential stage during the negative load current step from 100 mA to 0 A.…”

mentioning

confidence: 99%

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A CMOS low dropout regulator for internet of things

Jiang¹

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A wide input voltage range, high power supply rejection low‐dropout regulator with a closed‐loop charge pump for sensor front‐end circuits

Niu

Lai

Wang

2023

Circuit Theory & Apps

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SummaryThis paper presents a low dropout regulator (LDO) with a wide input voltage range and high power supply rejection (PSR) for Hall sensor front‐end circuits, which is fabricated with a 0.18 μm BCD process. A topology in which a closed‐loop charge pump biases the gate of two‐stage cascode NMOS pass transistors is proposed to increase immunity to electromagnetic interference (EMI) capability for automotive applications. Furthermore, a power‐down protection circuit is proposed to maintain the reliability of the system, and a novel implementation of the charge pump unit is presented to improve the influence of the body effect. Detailed derivation regarding the analyses of the simplified small‐signal model of the closed‐loop charge pump, the loop stability, and the PSR at various frequency bands is given. Simulation and measurement results show that the proposed LDO can operate with the input voltage from 5 to 40 V, providing up to 60 mA current drive capability, and its minimum operating voltage is 2.5 V with a 10 mA load capacity. Moreover, results verify that measured PSR is better than −45 dB at 1.5 kHz, and measured PSR is better than −30 dB at 15 MHz. The results confirm that the obtained parameters of line and load regulations are significantly improved to 1.86 mV/V and 1.75 mV/mA, respectively.

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