A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique

Choi, Donggwi; Kim, Dasom; Cho, Kyuik; Kim, Daeyun; Song, Minkyu

doi:10.1109/socdc.2010.5682940

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…The performance of the analog window detection circuit built on a 90nm CMOS process is compared with examples of other published decision circuits in Table 1 [9], [10], [15]- [23]. In the table, analog indices like supply voltage, input signal level, power penalty, capacity/P ratio, data rate and sampling frequency are considered.…”

Section: Comparison Of Performance Metricsmentioning

confidence: 99%

A window detection technique with adjustable threshold for transmitted reference receivers

Roy

Rashid

2012

Open Engineering

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This paper presents a threshold decision circuit with an adjustable detection window designed in a 90-nm IBM CMOS technology. Together with an RF mixer, the decision Section realizes the circuit implementation of the back-end of a transmitted reference ultra wideband receiver, which is yet to be reported in literature. The proposed circuit is built on a differential amplifier core and avoids the use of integrator and sampling blocks, which reduces the device burden necessary for the architecture. Moreover, the detection window threshold of the design can be regulated by three independent factors defined by the circuit elements. The circuit is tested at an input data rate of 0.1∼2.0 Gbps and the core decision section consumes 9.14 mW from a 1.2-V bias supply (with a maximum capacity/P ratio of 218.8 GHz/W). When compared against other reported decision blocks, the proposed detection circuit shows improved performance in terms of capacity and power requirement.

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Section: Comparison Of Performance Metricsmentioning

confidence: 99%

A window detection technique with adjustable threshold for transmitted reference receivers

Roy

Rashid

2012

Open Engineering

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“…The performance of the buffered window comparator in the back-end is tabulated in Table 2, illustrating its relative merits with respect to data rate, power dissipation, speed/power ratio, and supply voltage. To quantify the relative simulated performance of the proposed decision block with respect to published detection circuits [39][40][41][42][43][44][45][46][47][48][49], a second figure-of-merit (FOM 2 ) is defined with…”

Section: Isrn Electronicsmentioning

confidence: 99%

High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

Roy

2012

ISRN Electronics

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A new microwave receiver configuration which transmits reference pulses embedded in data streams for synchronization is analyzed with a 90-nm IBM CMOS standard. A two-stage cascode low-noise amplifier (LNA) is proposed for the receiver front-end which is matched by a passive network to save on power-expensive matching techniques. The amplifier exploits a double-differential topology and achieves a below 4 dB noise figure near the center frequency. The overall 3-dB bandwidth is 3.3 GHz with peaking up to 20.5 dB in the -band. The back-end of the receiver is implemented through an adjustable analog window-detection circuit. It avoids the use of control voltage generators and sample-hold (S/H) blocks to save electronic overhead and is simulated with a 0.1~2.0 Gbps pulse stream. The achieved speed-to-power ratio for the back-end has a maximum limit of 266 GHz/W. When compared against simulated results of published literature, the proposed designs show improved performance in terms of small-signal gain, noise, speed, and power dissipation.

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“…The performance of the analog window comparator using 90nm CMOS process is compared in table 1 with examples of other published comparators or ADCs [8,10,[12][13][14][15][16][17]. To make the comparison in terms of an analog decision circuit indices like supply voltage, input signal level, power penalty, speed to power ratio, data rate and sampling frequency are considered.…”

Section: Performance Metrics Of the Proposed Designmentioning

confidence: 99%

A threshold detection circuit using 90 nm CMOS technology for TR-UWB receivers

Roy¹,

Rashid²

2011

Active RF Devices, Circuits and Systems Seminar

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This paper presents a threshold detection circuit with an adjustable detection window designed in IBM 90nm CMOS technology. Together with a RF multiplier, it realizes the back-end section of a transmitted reference ultra wideband receiver, which is yet to be reported in literature. The comparator section uses an operational trans-conductance amplifier core and avoids the use of sample and hold and control voltage generator circuits which reduces the electronic overhead needed for the architecture. The design is tested at a bit rate of 0.1∼2.0Gbps and the decision circuit consumes 9.14mW power from a 1.2V bias supply with a maximum speed to power ratio of 218.8GHz/W. When compared against other reported comparators, the detection circuit shows improved performance in terms of speed and power dissipation.

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A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique

Cited by 4 publications

References 6 publications

A window detection technique with adjustable threshold for transmitted reference receivers

A window detection technique with adjustable threshold for transmitted reference receivers

High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

A threshold detection circuit using 90 nm CMOS technology for TR-UWB receivers

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