A low-noise CMOS preamplifier operating at 4.2 K

Kleine, U.; Bieger, J.; Seifert, Hans Jürgen

doi:10.1109/4.297696

Cited by 15 publications

(7 citation statements)

References 8 publications

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“…Cryogenic CMOS circuits have been proposed before for applications ranging from space missions to low-noise amplifiers (LNAs) [9]- [11]. However, quantum processors require extremely high performance from the classical electronic controller in terms of bandwidth and noise, so as to ensure accuracy and speed in the control and readout of the qubits.…”

mentioning

confidence: 99%

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

Patra

Incandela

Dijk

et al. 2018

IEEE J. Solid-State Circuits

357

169

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A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F 2,3 digitally controlled oscillator required to manipulate the state of qubits.

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mentioning

confidence: 99%

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

Patra

Incandela

Dijk

et al. 2018

IEEE J. Solid-State Circuits

357

169

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“…From the classical Drift Diffusion (DD) theory, the bipolar collector current is given in (3) where I C0 is the saturation collector current and V T = k B T/q the thermal voltage with k B the Boltzmann constant, T the temperature in Kelvin and q the electron electrical charge absolute value.…”

Section: Theorymentioning

confidence: 99%

“…Current Gain β Figure 2 represents the low frequency dynamic current gain (β AC = ∆I C /∆I B ) of the HBT0.8 versus collector current on a logarithmic scale at 300 K, 77 K and 4 K. For this HBT, the current gain decreases at low temperature, even if the presence of Germanium in the base attenuates this effect [3]. Indeed, for a standard Si Bipolar Junction Transistors (BJT), the current gain decreases at low temperature because of a factor e -∆Eg/kT where ∆Eg is the band-gap reduction in the heavily doped emitter and kT the thermal energy.…”

Section: Measurementsmentioning

confidence: 99%

“…Although SiGe technologies are often used for high frequency applications and although there are specific SiGe technologies optimised for working at cryogenic temperatures [2], our study reports some results on electrical DC and low frequency characterisations at 4 K obtained on HBTs for two different standard BiCMOS SiGe technologies that are not optimised for cryogenic applications. MOS transistors can also operate at cryogenic temperature [3], but they present higher Flicker …”

Section: Introductionmentioning

confidence: 99%

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Cryogenic SiGe Hetero-Junction Bipolar Transistors From Standard Technologies For Low Noise FLL

Prêle

Sou

Klisnick

et al. 2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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Dynamic range of Superconducting QUantum Interference Devices (SQUID) can be considerably increased by using a Flux-Locked-Loop (FLL). The FLL noise is mainly determined by the amplifier noise used in the feedback loop. The use of a very low noise amplifier working at cryogenic temperature can lead to reach the limit of SQUID intrinsic noise (typically few 10 -6 Φ 0 / Hz ). To realise the amplifier of the FLL, the use of standard technologies allows to design an ASIC including several amplifiers which are necessary for the read-out of a SQUID array. We present here some experimental results showing that two different standard BiCMOS SiGe technologies can operate at 4 K. DC and low frequency measurements were carried out on two SiGe Heterojunction Bipolar Transistors (HBT) of 0.8 µm and 0.35 µm AMS BiCMOS SiGe technologies. We report that for both SiGe HBTs, the transconductance gm increases at cryogenic temperatures making possible the use of such devices down to 4 K for low noise voltage amplification. However, the current gain β remains highly dependant on the fabrication process. Thus, we found that the current gain of the 0.8 µm technology HBTs decreases at low temperature whereas it increases for the 0.35 µm technology. The discussion is centred on the effects which could explain the behaviours of β and gm at temperature down to 4 K. Noise measurements are also presented confirming the existence of an effective temperature which increases the noise expected at 4 K. The presented results can lead to the realisation of cryogenic ASICs for low noise FLL readout of bolometers arrays dedicated to Cosmic Microwave Background (CMB) observations.

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“…However, by relying on the progress of semiconductor technology, only CMOS technology can currently offer the integration of billions of transistors on a single chip, while ensuring low-power consumption, reliability, and functionality down to 30 mK. 113 Beside simple cryogenic CMOS amplifiers, 26,27,114 complex cryogenic analog circuits have been implemented in CMOS, including a full 400 MHz transceiver operating at 173 K 115 and several 4 K analog-to-digital converters (ADC), such as successive approximation register (see Note), 116 Sigma Delta, 117 and Flash ADCs. 76 However, such devices operate at a relatively high temperature (»4 K) or they show poor power efficiency.…”

Section: Scalable Classical Cmos Control Electronics For Fault-toleramentioning

confidence: 99%

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

et al. 2017

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Even the quantum simulation of an apparently simple molecule such as Fe 2 S 2 requires a considerable number of qubits of the order of 10 6 , while more complex molecules such as alanine (C 3 H 7 NO 2 ) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for faulttolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal-oxide-semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal-oxide-semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal-oxide-semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal-oxide-semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via timedivision, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm 2 for the 10 and 7-...

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A low-noise CMOS preamplifier operating at 4.2 K

Cited by 15 publications

References 8 publications

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

Cryogenic SiGe Hetero-Junction Bipolar Transistors From Standard Technologies For Low Noise FLL

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

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