A Low-Noise Design Technique for High-Speed CMOS Optical Receivers

Li, Dan; Minoia, Gabriele; Repossi, Matteo; Baldi, Daniele; Temporiti, Enrico; Mazzanti, Andrea; Svelto, F.

doi:10.1109/jssc.2014.2322868

Cited by 134 publications

(54 citation statements)

References 17 publications

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“…A moderately higher performance is achieved by RX systems working with 1.3 μm wavelength such as [10] and [11] since these PD have a very low capacitance and very high responsivity. However 1.3 μm systems overall have the disadvantages on the transmitter side.…”

Section: Discussionmentioning

confidence: 99%

A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS

Szilágyi

Henker

Ellinger

2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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This paper presents the design, electrical and optical measurements of a receiver for optical communications in 28 nm CMOS. Electrical measurements show an error-free transmission with a bit error rate (BER) of 10 -12 up to 20 Gbps. Inductor-less peaking methods are used, thus the circuit is very compact. With only 0.0025 mm 2 , 13.6 mW power consumption, yielding 0.68 pJ/bit it is one of the smallest and most energy efficient receiver to this date for 20 Gbps data rate (DR). The receiver was bonded to a printed circuit board (PCB) and to a 14 Gbps, 850 nm photo diode. An error-free transmission over the optical link was obtained up to 17 Gbps with an input optical sensitivity of -4.3 dBm. The measured sensitivity at 15 Gbps is just -7.5 dBm and -8.4 dBm for 10 Gbps.

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Section: Discussionmentioning

confidence: 99%

A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS

Szilágyi

Henker

Ellinger

2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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“…2, incorporates the modified regulated-cascode (M-RGC) configuration in which a common-gate (CG) amplifier and a common-source (CS) amplifier with shunt resistive feedback are judiciously merged to achieve fully differential signaling at both drain nodes. Typically, TIAs can provide differential output voltages from a single-ended input current either by employing a passive lowpass filter (LPF) or by exploiting a replica input [6][7]. However, both cases cannot obtain fully differential signaling.…”

Section: Circuit Descriptionmentioning

confidence: 99%

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

Kim

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dB transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10 -12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm 2 including pad.

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“…The typical TIA usually utilize the two kinds of pseudo-differential structure by employing a passive low pass filter (LPF) [9,17] or exploiting a replica input [18,19], but both cases cannot obtain fully differential signal and have nonignorable defects. The passive low pass filter is not good for low frequency and long "1" data signal transmission and the replica input would greatly increase the chip area and power consumption.…”

Section: Introductionmentioning

confidence: 99%

A single-to-differential broadband transimpedance amplifier for 12.5 Gb/s optical links

Gao

Xie

Mao

et al. 2017

IEICE Electron. Express

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A broadband transimpedance amplifier (TIA) is designed and analyzed based on Regulated Cascode (RGC) configuration with L-matching network and cascode amplifier. A novel single-to-differential amplifier is also designed to simplify the following limiting amplifier (LA) design and increase the immunity of common-mode noise. The TIA is implemented in UMC 0.18 µm standard CMOS process. The measured transimpedance gain is 57 dBΩ with a −3 dB bandwidth of 8.1 GHz. The average equivalent input noise current spectral density is 29 pA/√Hz. The chip consumes 68 mW DC power under 1.8 V and occupies the area of 0.9 mm 2 .

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A Low-Noise Design Technique for High-Speed CMOS Optical Receivers

Cited by 134 publications

References 17 publications

A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS

A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

A single-to-differential broadband transimpedance amplifier for 12.5 Gb/s optical links

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