A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques

Khashaba, Amr; Elkholy, Ahmed; Megawer, Karim M.; Ahmed, Mostafa Gamal; Hanumolu, Pavan Kumar

doi:10.1109/jssc.2019.2951384

Cited by 7 publications

(5 citation statements)

References 14 publications

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“…In this prototype, a single ×2 PF unit, as shown in Fig. 16(a), consisting of two CMOS XOR gates and a differential buffer stage, accepts the 90 • -separated quadrature input phases [50]. The output is a 50% duty-cycle square wave at twice the input frequency.…”

Section: Phase Folding Logicmentioning

confidence: 99%

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Nguyên

Schembari

Staszewski

2022

IEEE J. Solid-State Circuits

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This article demonstrates the potential of deepsubthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm 2 and consumes 15.9 µW, resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

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Section: Phase Folding Logicmentioning

confidence: 99%

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Nguyên

Schembari

Staszewski

2022

IEEE J. Solid-State Circuits

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“…Table 2 presents a summary of the performances of the proposed crystal oscillator and a comparison with previous works [22,32,40,41]. A close analysis of the data in the table reveals that the phase noise of the crystal oscillator in this paper surpasses those found in similar research.…”

Section: Discussionmentioning

confidence: 55%

“…To achieve low phase noise in a crystal oscillator, several measures need to be taken to reduce noise contributions from various sources, such as the amplifier flicker noise, resonator flicker noise, resistor thermal noise, power supply noise, and nonlinear effects of the crystal [29][30][31]. In the future, researchers can focus on developing crystal oscillators with ultra-low phase noise [32,33], minimal frequency and temperature drift [34,35], fast start-up [36,37], and ultra-low power consumption [38,39], in order to cater to various application scenarios.…”

Section: Discussionmentioning

confidence: 99%

A Low Phase Noise Crystal Oscillator with a Fast Start-Up Bandgap Reference for WLAN Applications

Chen

et al. 2023

Applied Sciences

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This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a bandgap reference circuit that includes a start-up circuit and a low-voltage common-source common-gate current mirror, which ensures that the bandgap reference circuit is powered up effectively across all temperatures and process corners. A low-pass filter is also incorporated at the low dropout regulator (LDO) input to reduce the phase noise of the XO circuit. The experimental results demonstrate that the proposed design achieves a final phase noise of −164.36 dBc/Hz at 100 kHz offset frequency, with a power consumption of 0.444 mW. The test of start-up time is 0.718 ms and the compact chip area is 0.088 mm2. According to the simulation and test results, the final FOM value calculated in this paper is 209.93 dBc/Hz at 100 kHz offset.

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“…From a base unit ∆, the synthesizer first creates two types of cycles TA and TB. Their length-in-times are given by (1), where I is an integer. When synthesizing a particular frequency fs (period TTAF), it uses TA and TB in an interweaving fashion.…”

Section: Brief Review On Taf-dpsmentioning

confidence: 99%

“…In the past decades, clock is mostly used in the fixedfrequency style with high-frequency-stability as its highest priority. In clock-circuit design, people have focused almost their full attention on minimizing clock jitter and lowering phase noise [1][2][3][4][5][6][7][8][9]. When used in applications, such clock signal however has only few useable frequency choices.…”

Section: Introductionmentioning

confidence: 99%

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

Wei

Xiu

2022

IEEE Access

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Clock is the most important signal in electronic system. In current practice, the dominant clocking style is the fixed-frequency approach. For a given application, the clock signal is only required to work at a few selected frequencies. Moreover, in the process of performing a task, it must not change its frequency. This style has worked well in the past. However, it is preventing information processing efficiency from being raised to next level. Worse yet, the emergence of resource-constrained applications, such as edge computing and IoT, can render this approach unserviceable. In this paper, a new perspective of flexible clocking ideology is advocated. It promotes the use of a clock generator, TAF-DPS, that possesses features of "arbitrary frequency generation" and "instantaneous frequency switching". Owing to its superior capability in synthesizing waveform, TAF-DPS can handle many signal processing problems in a more elegant manner and serve some special purposes more efficiently. Further, it can be used for generating data for security purposes. TAF-DPS is especially applicable for environments with large frequency instability, which is a major problem in resource-constrained applications. The contribution of this paper is the advocacy of a new perspective of flexible clocking. This ideology is gradually developed in this paper as the argument is carried out through examples of novel architectures enabled by TAF-DPS. The perspective naturally emerges from the collective effect of those novel architectures. The large number of emerging applications, exemplified by edge computing and IoT, inspire system-level innovations that inevitably present new challenges to circuitlevel. Those challenges are so demanding that they require overhaul in our circuit design philosophy. This new perspective is such an overhaul in fundamental level. Its aim is to answer the challenges, for better serving the emerging demands in higher levels.

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A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques

Cited by 7 publications

References 14 publications

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

A Low Phase Noise Crystal Oscillator with a Fast Start-Up Bandgap Reference for WLAN Applications

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

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