A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Abstract

The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.

A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications

“…LVT kept a higher VDD/VTH ratio than standard VTH (SVT) or high VTH (HVT) transistors operation. As result, the proportionate changes in temperature from SVT to HVT are much larger as compared with that from LVT to SVT 19,44 . Therefore, using LVT transistors operation helps in stabilizing the power dissipation of our circuit against PVT for six different corners 19,45,46 …”

“…As result, the proportionate changes in temperature from SVT to HVT are much larger as compared with that from LVT to SVT. 19,44 Therefore, using LVT transistors operation helps in stabilizing the power dissipation of our circuit against PVT for six different corners. 19,45,46 As depicted in Figure 13, the power dissipation for the 85 C temperature is kept below 60 μW for the different corners.…”

Review of Four Improving Designs of Dynamic Latch Comparator

“…Figure 4. block diagram of the proposed dynamic comparator [2], and the proposed dynamic comparator structure Though the double-tail design outweighs the traditional comparator design, the J´erˆome K. Folla, Laboratory of Energy with his group introduced a new design called dynamic latch comparator with a higher gain and lower offset compared to double tail design, as shown in Figure 4. By applying a differential pair amplifier that contains enhanced load NMOS, the dynamic latch design will have lower power consumption and higher comparison speed.…”

“…In 2019, Mehrdad Amirkhan Dehkordi and his team proposed the double-tail structure of the dynamic latch comparator. By firstly introducing the double-stage design that contains the preamplifier stage and the latch stage, the double-tail design achieved a lower energy consumption [2]. However, though the circuit uses a time-domain bulk tuned offset cancellation technique to decrease the offset voltage that reduces energy consumption, the circuit is also slower than similar designs because of that [3][4].…”

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

“…Along with the advantages, the CMOS has also brought up some inevitable challenges for the designers, which include short channel effects, gate leakage, fabrication difficulty, sensitivity to process variations at nanoscale, etc. [5,6]. With the adaptation of the internet of things (IoT), battery-powered devices such as mobile phones, personal digital assistants (PDAs), and smartwatches are nowadays gaining much popularity around the world.…”