A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory

Abstract

Abstract-Multi-core prototyping presents a good opportunity for establishing low overhead and detailed profiling and visualization in order to study new research topics. In this paper, we design and implement a low execution, low area overhead profiling mechanism and a visualization tool for observing Transactional Memory behaviors on FPGA. To achieve this, we non-disruptively create and bring out events on the fly and process them offline on a host. There, our tool regenerates the execution from the collected events and produces traces for comprehensively inspecting the behavior of interacting multithreaded programs. With zero execution overhead for hardware TM events, single-instruction overhead for software TM events, and utilizing a low logic area of 2.3% per processor core, we run TM benchmarks to evaluate various different levels of profiling detail with an average runtime overhead of 6%. We demonstrate the usefulness of such detailed examination of SW/HW transactional behavior in two parts: (i) we speed up a TM benchmark by 24.1%, and (ii) we closely inspect transactions to point out pathologies.

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

“…With this new infrastructure in place, a complete cycle-accurate overview of the TM behavior of an application running on several processor cores can be obtained and analyzed [79]. A visual depiction of the runtime behavior of a TM program enables the viewer to easily identify application parts with different characteristics and to detect parts with sub-optimal behavior [8]. This can allow for specifically optimizing the poorly performing parts of the underlying TM system.…”