A Low Phase Noise and Wide-Bandwidth BiCMOS SiGe:C 0.25μm Digital Frequency Divider For An On-Chip Phase-Noise Measurement Circuit

Low Phase Noise Digital Division by 2 and by 3 of a 30 GHz Coupled Optoelectronic Oscillator

“…The designed divider by 2 is a DFF with the inverted output connected back to the input. A specific topology [4] In this case, the usual D latch current source is realized with a current mirror using MOS transistors. During the simulations, we ranked the components of the circuit according to their noise contribution and we noticed that the main noise contributors were the MOS transistors used as current sources in the D latches.…”

“…This divider was validated for an input frequency of 3.5 GHz [4], so the purpose is to demonstrate its functionality at much higher frequency, in this case up to 30 GHz. An optimization is done on the size of transistors, in order to lower the divider's residual noise as much as possible while ensuring a working frequency higher than 30 GHz.…”

An integrated phase noise measurement bench for on-chip characterization of resonators and VCOs

“…However, such a digital circuit located at a critical stage of the phase bridge can be the main noise source of the system. Our goal has thus been to optimize the phase noise of this circuit [6], in order to get a very low residual phase noise divider. This has been performed using the phase noise simulation capabilities of Cadence TM , and particularly the ability of this software to isolate the main noise source of the circuit.…”

“…An important optimization work has been focused on the D flip-flop topology, and more precisely on the current source of this differential element. More details on this process can be found in reference [6]. Figure 3 represents the realized circuit, and Figure 4 its residual phase noise simulated using Cadence TM and measured on a conventional (macroscopic) phase noise measurement set-up.…”