A low power 12 bit flux shuttle shift register with Nb technology

Lochschmied, R.; Herwig, R.; Neuhaus, M.; Jutzi, W.

doi:10.1109/77.621945

Cited by 14 publications

(6 citation statements)

References 14 publications

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“…A shuttle-flux shift register (SF-SR) was demonstrated in [27]. This circuit consists of three interferometers with three loops per bit.…”

Section: Sfq Shuttle Fluxmentioning

confidence: 99%

“…Our implementation of a single-stage SF-SR extends prior art [23], [25], [27], [36] and is illustrated in Fig. 4.…”

Section: Circuit Design Description a Implementation Of Single-stage ...mentioning

confidence: 99%

“…N shifting stages: The master cell consists of three magnetically-coupled interferometers, as shown in Fig. 4(b), where R1, R2, and R3 are the bias resistors connected to the three-phase input clock pulses [27]. An interferometer is a series structure of SQUIDs inductively coupled to one of the control lines [25].…”

Section: Circuit Design Description a Implementation Of Single-stage ...mentioning

confidence: 99%

“…To that end, we consider various shift register implementations based on RSFQ [11], [12], [21], quantum flux parametric (QFP) [22], and shuttle flux [23]- [26]. Among those three designs, shuttle flux-based designs have demonstrated a larger operating margin for each shifting operation [27]. Based on this exploration, we propose a shuttle-flux shift register (SF-SR) design based on scalable magnetically-coupled shuttle flux SQUIDs.…”

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confidence: 99%

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Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Bautista

Gonzalez-Guerrero

Lyles

2023

IEEE Trans. Circuits Syst. I

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This paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6µW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

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“…A shuttle-flux shift register (SF-SR) was demonstrated in [27]. This circuit consists of three interferometers with three loops per bit.…”

Section: Sfq Shuttle Fluxmentioning

confidence: 99%

“…Our implementation of a single-stage SF-SR extends prior art [23], [25], [27], [36] and is illustrated in Fig. 4.…”

Section: Circuit Design Description a Implementation Of Single-stage ...mentioning

confidence: 99%

Section: Circuit Design Description a Implementation Of Single-stage ...mentioning

confidence: 99%

mentioning

confidence: 99%

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Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Bautista

Gonzalez-Guerrero

Lyles

2023

IEEE Trans. Circuits Syst. I

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“…Shift registers are the most natural RSFQ circuits as RSFQ is a sequential logic rather than a combinational logic such as CMOS. A number of RSFQ shift registers designs were developed in the past [36][37][38][39][40][41][42][43][44]. The most robust and widespread design consists of D flip-flops with an integrated SFQ clock network [39], which we chose for implementation in eSFQ logic.…”

Section: Design Of Esfq Shift Registersmentioning

confidence: 99%

Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation

Volkmann

Sahu

Fourie

et al. 2012

Supercond. Sci. Technol.

142

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We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm 2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.

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Platinum thin film resistors with Cr under- and overlayers for Nb/Al2O3/Nb technology

Dolata

Balashov

1998

Physica C: Superconductivity

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A low power 12 bit flux shuttle shift register with Nb technology

Cited by 14 publications

References 14 publications

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation

Platinum thin film resistors with Cr under- and overlayers for Nb/Al2O3/Nb technology

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